# AND gate

Canonical URL: https://eloragrid.ai/symbols/logic-and-gate
Publisher: Elora Grid
Updated: 2026-10-14
Lookup label: AND
Drawing use: Schematic
Reference families: Manufacturer

A logic element whose output is true when all stated positive-logic inputs are true.

## What it represents

A logic element whose output is true when all stated positive-logic inputs are true.
On a schematic, identify the input signal polarity and the required simultaneous conditions and trace the gate output and its destination. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
An AND gate combines logical conditions; it does not specify relay-contact current capacity or a safety integrity level.
Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.

## How to read it

- Identify the input signal polarity and the required simultaneous conditions.
- Trace the gate output and its destination.

## Information to show or reference

- Label the input signal polarity and the required simultaneous conditions.
- Cross-reference the gate output and its destination.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.

## Important distinction

An AND gate combines logical conditions; it does not specify relay-contact current capacity or a safety integrity level.

## Facts

- Common schematic mnemonic: AND — descriptive only; project/device documentation defines reference designations.
- Terminal / interface focus: The input signal polarity and the required simultaneous conditions
- Artwork scope: Original educational component glyph; not a certified standard graphic or package pinout.

## Public references

- [SN74HC08 — AND gate logic](https://www.ti.com/lit/ds/symlink/sn74hc08.pdf) — Texas Instruments. Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.