{"schemaVersion":1,"slug":"logic-or-gate","name":"OR gate","kind":"symbol","abbreviation":"OR","aliases":["inclusive OR","logical OR"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["Manufacturer"],"summary":"A positive-logic element whose output is true when at least one input is true.","description":["A positive-logic element whose output is true when at least one input is true.","On a schematic, identify the input signal meanings and the inclusive-OR convention and trace the combined permissive or alarm output. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.","Inclusive OR differs from XOR: OR remains true when both inputs are true.","Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing."],"readingNotes":["Identify the input signal meanings and the inclusive-OR convention.","Trace the combined permissive or alarm output."],"drawingChecklist":["Label the input signal meanings and the inclusive-OR convention.","Cross-reference the combined permissive or alarm output.","Add the selected device or circuit documentation revision, power/reference connections and project signal convention."],"distinction":"Inclusive OR differs from XOR: OR remains true when both inputs are true.","facts":[{"label":"Common schematic mnemonic","value":"OR — descriptive only; project/device documentation defines reference designations."},{"label":"Terminal / interface focus","value":"The input signal meanings and the inclusive-OR convention"},{"label":"Artwork scope","value":"Original educational component glyph; not a certified standard graphic or package pinout."}],"references":[{"sourceId":"pub-electronics-ti-hc32","relevance":"Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored."}],"related":["logic-xor-gate","plc-io"],"artwork":"electronics-gate-or","publishedOn":"2026-10-14","updatedOn":"2026-10-14","provenance":"independent-public-research","url":"https://eloragrid.ai/symbols/logic-or-gate","illustration":{"url":"https://eloragrid.ai/library/illustrations/logic-or-gate.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"pub-electronics-ti-hc32","title":"SN74HC32 — OR gate logic","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ds/symlink/sn74hc32.pdf","type":"manufacturer","scope":"Public device-function and terminal documentation used as an example of or gate logic. Example part numbers are manufacturer identifiers, not IEC/IEEE symbol IDs. Device ratings, pin numbering and availability remain in the selected product documentation.","checkedOn":"2026-10-14","reuse":"link-only","relevance":"Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored."}]}