# P-channel JFET

Canonical URL: https://eloragrid.ai/symbols/p-channel-jfet
Publisher: Elora Grid
Updated: 2026-10-14
Lookup label: P-JFET
Drawing use: Schematic
Reference families: Manufacturer

A junction field-effect transistor using a P-type channel and the corresponding gate-bias polarity.

## What it represents

A junction field-effect transistor using a P-type channel and the corresponding gate-bias polarity.
On a schematic, identify the gate junction polarity and drain/source references and trace the analogue control or amplifier path. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
P-channel and N-channel JFETs use opposite gate-bias polarity; the arrow and manufacturer terminal diagram resolve the type.
Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.

## How to read it

- Identify the gate junction polarity and drain/source references.
- Trace the analogue control or amplifier path.

## Information to show or reference

- Label the gate junction polarity and drain/source references.
- Cross-reference the analogue control or amplifier path.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.

## Important distinction

P-channel and N-channel JFETs use opposite gate-bias polarity; the arrow and manufacturer terminal diagram resolve the type.

## Facts

- Common schematic mnemonic: P-JFET — descriptive only; project/device documentation defines reference designations.
- Terminal / interface focus: The gate junction polarity and drain/source references
- Artwork scope: Original educational component glyph; not a certified standard graphic or package pinout.

## Public references

- [JFET master table with explicit P-channel device classification](https://interfet.com/jfet-master-table/) — InterFET. Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.