{"schemaVersion":1,"slug":"positive-edge-d-flip-flop","name":"Positive-edge D flip-flop","kind":"symbol","abbreviation":"D-FF","aliases":["D type flip flop","edge triggered storage"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["Manufacturer"],"summary":"Captures its data input at the documented positive clock edge and retains that digital state.","description":["Captures its data input at the documented positive clock edge and retains that digital state.","On a schematic, identify the D input, clock edge and asynchronous preset/clear polarities and trace the stored Q output and any complemented output. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.","An edge-triggered flip-flop differs from a transparent latch; data timing relative to the clock remains essential.","The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing."],"readingNotes":["Identify the D input, clock edge and asynchronous preset/clear polarities.","Trace the stored Q output and any complemented output."],"drawingChecklist":["Label the D input, clock edge and asynchronous preset/clear polarities.","Cross-reference the stored Q output and any complemented output.","Add the selected device or circuit documentation revision, power/reference connections and project signal convention."],"distinction":"An edge-triggered flip-flop differs from a transparent latch; data timing relative to the clock remains essential.","facts":[{"label":"Common schematic mnemonic","value":"D-FF — descriptive only; project/device documentation defines reference designations."},{"label":"Terminal / interface focus","value":"The D input, clock edge and asynchronous preset/clear polarities"},{"label":"Artwork scope","value":"Original educational functional/circuit reference; not a selected product pinout."}],"references":[{"sourceId":"pub-electronics-ti-hc74","relevance":"Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored."}],"related":["transparent-d-latch","plc-io"],"artwork":"electronics-memory-dff","publishedOn":"2026-10-14","updatedOn":"2026-10-14","provenance":"independent-public-research","url":"https://eloragrid.ai/symbols/positive-edge-d-flip-flop","illustration":{"url":"https://eloragrid.ai/library/illustrations/positive-edge-d-flip-flop.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"pub-electronics-ti-hc74","title":"SN74HC74 — positive-edge D flip-flops","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ds/symlink/sn74hc74.pdf","type":"manufacturer","scope":"Public device-function and terminal documentation used as an example of positive-edge d flip-flops. Example part numbers are manufacturer identifiers, not IEC/IEEE symbol IDs. Device ratings, pin numbering and availability remain in the selected product documentation.","checkedOn":"2026-10-14","reuse":"link-only","relevance":"Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored."}]}