# ANSI AND-OR-invert gate

Canonical URL: https://eloragrid.ai/symbols/ansi-and-or-invert-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: AOI
Drawing use: Schematic
Reference families: IEEE / ANSI, Manufacturer

## Symbol convention

Convention: IEEE / ANSI
Form: Two AND outlines feeding an OR outline with output bubble
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.

Two D-shaped AND gates feeding a bubbled OR outline, drawn as the distinctive-shape AND-OR-invert function.

## In plain English

### What does ANSI AND-OR-invert gate mean?

In distinctive-shape drawings the AND-OR-invert function is shown as two or more AND outlines whose outputs enter an OR outline with an output bubble. Data books often draw the AND outlines touching the OR outline to indicate that the whole structure is one gate within one package section.

### A simple example

AOI gates are found in older logic boards for multiplexing and for implementing compact sum-of-products expressions. When checking, write the expression as the complement of the OR of each AND term.

### What the drawings help you do

The drawing does not reveal whether the device provides expandable inputs or how unused AND inputs must be terminated. Refer to the device documentation for those details.

### This particular reference

Two D-shaped AND gates feeding a bubbled OR outline, drawn as the distinctive-shape AND-OR-invert function. The IEC AND-OR-invert uses abutted rectangular & and ≥1 elements instead of distinctive outlines.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [SN74LS51 AND-OR-invert gates](https://www.ti.com/lit/ds/symlink/sn74ls51.pdf)


## What it represents

In distinctive-shape drawings the AND-OR-invert function is shown as two or more AND outlines whose outputs enter an OR outline with an output bubble. Data books often draw the AND outlines touching the OR outline to indicate that the whole structure is one gate within one package section.
AOI gates are found in older logic boards for multiplexing and for implementing compact sum-of-products expressions. When checking, write the expression as the complement of the OR of each AND term.
The drawing does not reveal whether the device provides expandable inputs or how unused AND inputs must be terminated. Refer to the device documentation for those details.

## How to read it

- Treat touching outlines as one device function, not separate packages.
- Apply the final inversion after the OR.

## Information to show or reference

- Keep the AND sections visually grouped with the OR.
- Label each product-term input.
- Terminate unused AND inputs as the device requires.

## Important distinction

The IEC AND-OR-invert uses abutted rectangular & and ≥1 elements instead of distinctive outlines.

## Facts

- Structure: AND terms into OR with inverted output
- Example device family: Dual AND-OR-invert gate packages
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [SN74LS51 AND-OR-invert gates](https://www.ti.com/lit/ds/symlink/sn74ls51.pdf) — Texas Instruments. Manufacturer AND-OR-invert gate documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.