{"schemaVersion":1,"slug":"ansi-cross-coupled-nor-latch","name":"ANSI cross-coupled NOR latch","kind":"symbol","abbreviation":"SR","aliases":["NOR SR latch","active-high set-reset latch","cross-coupled NOR flip-flop"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["IEEE / ANSI","Manufacturer"],"summary":"Two NOR gates cross-coupled to form an SR latch with active-high set and reset inputs.","description":["Two NOR gates with each output fed back to an input of the other form an SR latch with active-high inputs. A high on set drives Q high, a high on reset drives Q low, and both low holds the state. Both high forces both outputs low and is normally treated as invalid.","This form appears in educational schematics and in discrete logic designs where a spare quad NOR package provides a latch. It is the natural form when the set and reset signals are active-high commands.","Like the NAND form, it shows construction rather than a guaranteed power-up state. A defined start-up condition needs extra circuitry or a reset pulse."],"readingNotes":["Inputs are active high.","Both inputs high gives both outputs low."],"drawingChecklist":["Draw feedback paths clearly.","Identify which output is Q.","Show the power-up reset arrangement if needed."],"distinction":"The cross-coupled NAND latch responds to active-low inputs.","facts":[{"label":"Input sense","value":"Active high"},{"label":"Invalid state","value":"Both inputs high"},{"label":"Artwork scope","value":"Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic"}],"references":[{"sourceId":"pub-electronics-ti-hc02","relevance":"NOR gate documentation for the building block."}],"related":["set-reset-latch","ansi-cross-coupled-nand-latch","iec-sr-latch"],"artwork":"s28-ansi-cross-coupled-nor-latch","publishedOn":"2026-10-28","updatedOn":"2026-10-28","provenance":"independent-public-research","symbolVariant":{"convention":"IEEE / ANSI","form":"Two NOR outlines with each output fed back to the other gate's input","reference":"Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.","counterpart":"set-reset-latch"},"plainEnglish":{"title":"What does ANSI cross-coupled NOR latch mean?","introduction":"Two NOR gates with each output fed back to an input of the other form an SR latch with active-high inputs. A high on set drives Q high, a high on reset drives Q low, and both low holds the state. Both high forces both outputs low and is normally treated as invalid.","example":"This form appears in educational schematics and in discrete logic designs where a spare quad NOR package provides a latch. It is the natural form when the set and reset signals are active-high commands.","drawings":"Like the NAND form, it shows construction rather than a guaranteed power-up state. A defined start-up condition needs extra circuitry or a reset pulse.","terms":[{"name":"Signal","meaning":"Electrical information passed between devices, rather than necessarily the main power supply."},{"name":"Schematic","meaning":"A drawing showing function and connections rather than physical appearance."}],"diagram":"flow","steps":["Identify the device and form","Read the connections and state","Check the equipment reference"],"caption":"A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.","sources":[{"label":"SN74HC02 — NOR gate logic","url":"https://www.ti.com/lit/ds/symlink/sn74hc02.pdf"}],"detail":"Two NOR gates cross-coupled to form an SR latch with active-high set and reset inputs. The cross-coupled NAND latch responds to active-low inputs.","profileId":"reviewed-symbol-20261028"},"url":"https://eloragrid.ai/symbols/ansi-cross-coupled-nor-latch","illustration":{"url":"https://eloragrid.ai/tools/electrical-library/illustrations/ansi-cross-coupled-nor-latch.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"pub-electronics-ti-hc02","title":"SN74HC02 — NOR gate logic","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ds/symlink/sn74hc02.pdf","type":"manufacturer","scope":"Public device-function and terminal documentation used as an example of nor gate logic. Example part numbers are manufacturer identifiers, not IEC/IEEE symbol IDs. Device ratings, pin numbering and availability remain in the selected product documentation.","checkedOn":"2026-10-14","reuse":"link-only","relevance":"NOR gate documentation for the building block."}]}