# ANSI inhibit gate (AND with one negated input)

Canonical URL: https://eloragrid.ai/symbols/ansi-inhibit-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: INH
Drawing use: Schematic
Reference families: IEEE / ANSI, Manufacturer

## Symbol convention

Convention: IEEE / ANSI
Form: AND outline with a bubble on one input
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.

AND outline with a bubble on one input, so that input blocks the output whenever it is active.

## In plain English

### What does ANSI inhibit gate (AND with one negated input) mean?

An inhibit gate passes one signal only while a second, inhibiting signal is inactive. In distinctive-shape form it is drawn as an AND outline with a bubble on the inhibiting input. It is a very common pattern in interlock logic, where a command is allowed unless a blocking condition is present.

### A simple example

On drawings the inhibiting input should be named for the condition that blocks, such as trip active or door open, so that the bubble reads naturally. Where the physical implementation is an AND gate fed by an inverter, the schematic may still use this compact form for clarity.

### What the drawings help you do

The symbol does not specify which input has priority in timing. If the inhibiting signal must arrive before the command, a sequencing note or timing element is required.

### This particular reference

AND outline with a bubble on one input, so that input blocks the output whenever it is active. A NAND has its bubble at the output; an inhibit gate has its bubble on one input only.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC08 — AND gate logic](https://www.ti.com/lit/ds/symlink/sn74hc08.pdf)


## What it represents

An inhibit gate passes one signal only while a second, inhibiting signal is inactive. In distinctive-shape form it is drawn as an AND outline with a bubble on the inhibiting input. It is a very common pattern in interlock logic, where a command is allowed unless a blocking condition is present.
On drawings the inhibiting input should be named for the condition that blocks, such as trip active or door open, so that the bubble reads naturally. Where the physical implementation is an AND gate fed by an inverter, the schematic may still use this compact form for clarity.
The symbol does not specify which input has priority in timing. If the inhibiting signal must arrive before the command, a sequencing note or timing element is required.

## How to read it

- Identify which input carries the bubble; that input blocks the output.
- Check whether the implementation includes a separate inverter.

## Information to show or reference

- Name the inhibiting input for the blocking condition.
- Place the bubble on the correct input lead.
- Note any timing priority between command and inhibit.

## Important distinction

A NAND has its bubble at the output; an inhibit gate has its bubble on one input only.

## Facts

- Boolean form: A AND NOT B
- Typical use: Command blocked by an interlock
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Negation at an input and the resulting internal state.
- [SN74HC08 — AND gate logic](https://www.ti.com/lit/ds/symlink/sn74hc08.pdf) — Texas Instruments. AND gate documentation for the implementing function.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.