{"schemaVersion":1,"slug":"ansi-nand-as-negative-or-gate","name":"ANSI NAND gate drawn as negative-input OR","kind":"symbol","abbreviation":"NAND","aliases":["De Morgan NAND form","OR with bubbled inputs","negative-OR symbol"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["IEEE / ANSI","Manufacturer"],"summary":"OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low.","description":["By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.","This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.","The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package."],"readingNotes":["Recognise bubbled inputs on an OR outline as a NAND device.","Expect the input nets to be active-low signals."],"drawingChecklist":["Use this form when the input signals are active low.","Keep the device reference the same as the NAND package.","Explain the convention in the sheet legend for unfamiliar readers."],"distinction":"An OR outline with a bubble at the output is a NOR, not this NAND equivalent.","facts":[{"label":"Boolean identity","value":"NOT(A AND B) = (NOT A) OR (NOT B)"},{"label":"Reason to use","value":"Matches active-low input signals"},{"label":"Artwork scope","value":"Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic"}],"references":[{"sourceId":"pub-electronics-ti-hc00","relevance":"Manufacturer NAND gate documentation for the implementing device."},{"sourceId":"s28-ti-ieee91-logic-symbols","relevance":"Explains negation and active-low indication at inputs."}],"related":["logic-nand-gate","ansi-four-input-nand-gate","ansi-nor-as-negative-and-gate"],"artwork":"s28-ansi-nand-as-negative-or-gate","publishedOn":"2026-10-28","updatedOn":"2026-10-28","provenance":"independent-public-research","symbolVariant":{"convention":"IEEE / ANSI","form":"OR outline with input bubbles (De Morgan equivalent of NAND)","reference":"Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.","counterpart":"logic-nand-gate"},"plainEnglish":{"title":"What does ANSI NAND gate drawn as negative-input OR mean?","introduction":"By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.","example":"This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.","drawings":"The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package.","terms":[{"name":"Signal","meaning":"Electrical information passed between devices, rather than necessarily the main power supply."},{"name":"Schematic","meaning":"A drawing showing function and connections rather than physical appearance."}],"diagram":"flow","steps":["Identify the device and form","Read the connections and state","Check the equipment reference"],"caption":"A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.","sources":[{"label":"SN74HC00 — NAND gate logic","url":"https://www.ti.com/lit/ds/symlink/sn74hc00.pdf"},{"label":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf"}],"detail":"OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low. An OR outline with a bubble at the output is a NOR, not this NAND equivalent.","profileId":"reviewed-symbol-20261028"},"url":"https://eloragrid.ai/symbols/ansi-nand-as-negative-or-gate","illustration":{"url":"https://eloragrid.ai/tools/electrical-library/illustrations/ansi-nand-as-negative-or-gate.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"pub-electronics-ti-hc00","title":"SN74HC00 — NAND gate logic","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ds/symlink/sn74hc00.pdf","type":"manufacturer","scope":"Public device-function and terminal documentation used as an example of nand gate logic. Example part numbers are manufacturer identifiers, not IEC/IEEE symbol IDs. Device ratings, pin numbering and availability remain in the selected product documentation.","checkedOn":"2026-10-14","reuse":"link-only","relevance":"Manufacturer NAND gate documentation for the implementing device."},{"id":"s28-ti-ieee91-logic-symbols","title":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf","type":"manufacturer","scope":"Public explanation of rectangular logic symbols, general qualifiers, input and output qualifiers, dependency notation, bistable elements and coders, consistent with IEC 617-12 work.","checkedOn":"2026-10-28","reuse":"link-only","relevance":"Explains negation and active-low indication at inputs."}]}