# ANSI NAND gate drawn as negative-input OR

Canonical URL: https://eloragrid.ai/symbols/ansi-nand-as-negative-or-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: NAND
Drawing use: Schematic
Reference families: IEEE / ANSI, Manufacturer

## Symbol convention

Convention: IEEE / ANSI
Form: OR outline with input bubbles (De Morgan equivalent of NAND)
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [NAND gate](https://eloragrid.ai/symbols/logic-nand-gate)

OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low.

## In plain English

### What does ANSI NAND gate drawn as negative-input OR mean?

By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.

### A simple example

This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.

### What the drawings help you do

The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package.

### This particular reference

OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low. An OR outline with a bubble at the output is a NOR, not this NAND equivalent.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [SN74HC00 — NAND gate logic](https://www.ti.com/lit/ds/symlink/sn74hc00.pdf)
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)


## What it represents

By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.
This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.
The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package.

## How to read it

- Recognise bubbled inputs on an OR outline as a NAND device.
- Expect the input nets to be active-low signals.

## Information to show or reference

- Use this form when the input signals are active low.
- Keep the device reference the same as the NAND package.
- Explain the convention in the sheet legend for unfamiliar readers.

## Important distinction

An OR outline with a bubble at the output is a NOR, not this NAND equivalent.

## Facts

- Boolean identity: NOT(A AND B) = (NOT A) OR (NOT B)
- Reason to use: Matches active-low input signals
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [SN74HC00 — NAND gate logic](https://www.ti.com/lit/ds/symlink/sn74hc00.pdf) — Texas Instruments. Manufacturer NAND gate documentation for the implementing device.
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Explains negation and active-low indication at inputs.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.