{"schemaVersion":1,"slug":"ansi-nor-as-negative-and-gate","name":"ANSI NOR gate drawn as negative-input AND","kind":"symbol","abbreviation":"NOR","aliases":["De Morgan NOR form","AND with bubbled inputs","negative-AND symbol"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["IEEE / ANSI","Manufacturer"],"summary":"AND outline with bubbled inputs, the De Morgan form of a NOR that reads as all inputs low gives a high output.","description":["A NOR gate is equivalent to an AND gate with inverted inputs. Drawing the AND outline with input bubbles states the design intent directly: the output is high only when all inputs are low. It is the same device as a NOR gate with the outline chosen to match the signal sense.","This representation is common for all-clear logic where each input is an active-high fault, so all-low means healthy. It also helps when reviewing permissive chains, because the outline reads as a conjunction of conditions.","As with any De Morgan form, the part fitted is still a NOR device. The parts list, pin numbering and gate section remain those of the NOR package."],"readingNotes":["Read bubbled inputs on an AND outline as a NOR device.","Confirm the part reference matches a NOR package."],"drawingChecklist":["Use the form consistently for active-low or all-clear logic.","Keep the NOR device reference.","Document the De Morgan convention in the legend."],"distinction":"An AND outline with only an output bubble is a NAND; here the bubbles are on the inputs.","facts":[{"label":"Boolean identity","value":"NOT(A OR B) = (NOT A) AND (NOT B)"},{"label":"Reason to use","value":"Reads as all inputs low"},{"label":"Artwork scope","value":"Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic"}],"references":[{"sourceId":"pub-electronics-ti-hc02","relevance":"Manufacturer NOR gate documentation for the implementing device."},{"sourceId":"s28-ti-ieee91-logic-symbols","relevance":"Negation at inputs."}],"related":["logic-nor-gate","ansi-three-input-nor-gate","ansi-nand-as-negative-or-gate"],"artwork":"s28-ansi-nor-as-negative-and-gate","publishedOn":"2026-10-28","updatedOn":"2026-10-28","provenance":"independent-public-research","symbolVariant":{"convention":"IEEE / ANSI","form":"AND outline with input bubbles (De Morgan equivalent of NOR)","reference":"Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.","counterpart":"logic-nor-gate"},"plainEnglish":{"title":"What does ANSI NOR gate drawn as negative-input AND mean?","introduction":"A NOR gate is equivalent to an AND gate with inverted inputs. Drawing the AND outline with input bubbles states the design intent directly: the output is high only when all inputs are low. It is the same device as a NOR gate with the outline chosen to match the signal sense.","example":"This representation is common for all-clear logic where each input is an active-high fault, so all-low means healthy. It also helps when reviewing permissive chains, because the outline reads as a conjunction of conditions.","drawings":"As with any De Morgan form, the part fitted is still a NOR device. The parts list, pin numbering and gate section remain those of the NOR package.","terms":[{"name":"Signal","meaning":"Electrical information passed between devices, rather than necessarily the main power supply."},{"name":"Schematic","meaning":"A drawing showing function and connections rather than physical appearance."}],"diagram":"flow","steps":["Identify the device and form","Read the connections and state","Check the equipment reference"],"caption":"A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.","sources":[{"label":"SN74HC02 — NOR gate logic","url":"https://www.ti.com/lit/ds/symlink/sn74hc02.pdf"},{"label":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf"}],"detail":"AND outline with bubbled inputs, the De Morgan form of a NOR that reads as all inputs low gives a high output. An AND outline with only an output bubble is a NAND; here the bubbles are on the inputs.","profileId":"reviewed-symbol-20261028"},"url":"https://eloragrid.ai/symbols/ansi-nor-as-negative-and-gate","illustration":{"url":"https://eloragrid.ai/tools/electrical-library/illustrations/ansi-nor-as-negative-and-gate.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"pub-electronics-ti-hc02","title":"SN74HC02 — NOR gate logic","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ds/symlink/sn74hc02.pdf","type":"manufacturer","scope":"Public device-function and terminal documentation used as an example of nor gate logic. Example part numbers are manufacturer identifiers, not IEC/IEEE symbol IDs. Device ratings, pin numbering and availability remain in the selected product documentation.","checkedOn":"2026-10-14","reuse":"link-only","relevance":"Manufacturer NOR gate documentation for the implementing device."},{"id":"s28-ti-ieee91-logic-symbols","title":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf","type":"manufacturer","scope":"Public explanation of rectangular logic symbols, general qualifiers, input and output qualifiers, dependency notation, bistable elements and coders, consistent with IEC 617-12 work.","checkedOn":"2026-10-28","reuse":"link-only","relevance":"Negation at inputs."}]}