# ANSI NOR gate drawn as negative-input AND

Canonical URL: https://eloragrid.ai/symbols/ansi-nor-as-negative-and-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: NOR
Drawing use: Schematic
Reference families: IEEE / ANSI, Manufacturer

## Symbol convention

Convention: IEEE / ANSI
Form: AND outline with input bubbles (De Morgan equivalent of NOR)
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [NOR gate](https://eloragrid.ai/symbols/logic-nor-gate)

AND outline with bubbled inputs, the De Morgan form of a NOR that reads as all inputs low gives a high output.

## In plain English

### What does ANSI NOR gate drawn as negative-input AND mean?

A NOR gate is equivalent to an AND gate with inverted inputs. Drawing the AND outline with input bubbles states the design intent directly: the output is high only when all inputs are low. It is the same device as a NOR gate with the outline chosen to match the signal sense.

### A simple example

This representation is common for all-clear logic where each input is an active-high fault, so all-low means healthy. It also helps when reviewing permissive chains, because the outline reads as a conjunction of conditions.

### What the drawings help you do

As with any De Morgan form, the part fitted is still a NOR device. The parts list, pin numbering and gate section remain those of the NOR package.

### This particular reference

AND outline with bubbled inputs, the De Morgan form of a NOR that reads as all inputs low gives a high output. An AND outline with only an output bubble is a NAND; here the bubbles are on the inputs.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [SN74HC02 — NOR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc02.pdf)
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)


## What it represents

A NOR gate is equivalent to an AND gate with inverted inputs. Drawing the AND outline with input bubbles states the design intent directly: the output is high only when all inputs are low. It is the same device as a NOR gate with the outline chosen to match the signal sense.
This representation is common for all-clear logic where each input is an active-high fault, so all-low means healthy. It also helps when reviewing permissive chains, because the outline reads as a conjunction of conditions.
As with any De Morgan form, the part fitted is still a NOR device. The parts list, pin numbering and gate section remain those of the NOR package.

## How to read it

- Read bubbled inputs on an AND outline as a NOR device.
- Confirm the part reference matches a NOR package.

## Information to show or reference

- Use the form consistently for active-low or all-clear logic.
- Keep the NOR device reference.
- Document the De Morgan convention in the legend.

## Important distinction

An AND outline with only an output bubble is a NAND; here the bubbles are on the inputs.

## Facts

- Boolean identity: NOT(A OR B) = (NOT A) AND (NOT B)
- Reason to use: Reads as all inputs low
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [SN74HC02 — NOR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc02.pdf) — Texas Instruments. Manufacturer NOR gate documentation for the implementing device.
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Negation at inputs.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.