# ANSI three-state inverter with active-low enable

Canonical URL: https://eloragrid.ai/symbols/ansi-three-state-inverter
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: OE
Drawing use: Schematic
Reference families: IEEE / ANSI, Manufacturer

## Symbol convention

Convention: IEEE / ANSI
Form: Inverter triangle with bubble and enable lead with bubble on the triangle side
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.

Inverter triangle with an enable lead and bubble entering its side, driving a bus only when enabled.

## In plain English

### What does ANSI three-state inverter with active-low enable mean?

The three-state inverter is a triangle with an output bubble and a control lead entering the sloping side. A bubble on the control lead means output enable is active low, which is the arrangement on many octal line drivers. When disabled, the output is high impedance.

### A simple example

On bus schematics these devices are usually drawn in groups of eight with a shared enable. Drafters should label the enable net once for the group and show which controller output drives it, so the reader can see when the bus is driven.

### What the drawings help you do

The symbol does not show bus hold, pull-up or pull-down arrangements needed to keep a disabled bus at a defined level. Those components must be drawn separately.

### This particular reference

Inverter triangle with an enable lead and bubble entering its side, driving a bus only when enabled. The non-inverting three-state buffer has no output bubble.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [SNx4HC240 octal buffers and line drivers with 3-state outputs](https://www.ti.com/lit/ds/symlink/sn74hc240.pdf)
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)


## What it represents

The three-state inverter is a triangle with an output bubble and a control lead entering the sloping side. A bubble on the control lead means output enable is active low, which is the arrangement on many octal line drivers. When disabled, the output is high impedance.
On bus schematics these devices are usually drawn in groups of eight with a shared enable. Drafters should label the enable net once for the group and show which controller output drives it, so the reader can see when the bus is driven.
The symbol does not show bus hold, pull-up or pull-down arrangements needed to keep a disabled bus at a defined level. Those components must be drawn separately.

## How to read it

- Check the bubble on the enable lead; it sets the enable polarity.
- Look for bus-keeper or pull resistors on the driven net.

## Information to show or reference

- Draw the enable lead touching the sloping side of the triangle.
- Mark enable polarity explicitly.
- Show the shared enable source for a group of drivers.

## Important distinction

The non-inverting three-state buffer has no output bubble.

## Facts

- Enable sense: Active low when the control lead has a bubble
- Disabled output: High impedance
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [SNx4HC240 octal buffers and line drivers with 3-state outputs](https://www.ti.com/lit/ds/symlink/sn74hc240.pdf) — Texas Instruments. Manufacturer documentation for inverting octal buffers with three-state outputs.
- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Three-state output and EN behaviour.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.