{"schemaVersion":1,"slug":"iec-and-dependency-g","name":"IEC AND dependency (G)","kind":"symbol","abbreviation":"Gm","aliases":["G dependency","AND dependency notation","Gm affecting input"],"category":"logic-signals","drawingTypes":["Schematic"],"referenceFamilies":["IEC","Manufacturer"],"summary":"Dependency label Gm: inputs or outputs carrying the number m are ANDed with the affecting G input.","description":["In dependency notation, an input labelled G followed by a number is an affecting input. Every input or output labelled with the same number is ANDed with it. When the G input is at its internal 1 state the affected signals act normally; at its internal 0 state they are forced to 0. A bar over the number means the complement of the G input affects them.","G dependency lets a device symbol show gating relationships without drawing extra AND gates. It is common on multiplexers, gated clocks and register symbols in device data books, and a drafter copying such a symbol must keep the numbers intact or the meaning changes.","The label describes logic only. It does not tell you whether the gating causes glitches on a clock line or what setup time applies between G and the affected input."],"readingNotes":["Match each G number to every input or output carrying that number.","A bar over the affected number means the complement of G applies."],"drawingChecklist":["Keep G numbers unique within a symbol.","Label every affected terminal with the matching number.","Avoid mixing G numbers with other dependency letters using the same number."],"distinction":"V (OR) dependency imposes a 1 state when the affecting input is 1; G imposes a 0 state when the affecting input is 0.","facts":[{"label":"Affecting input at 1","value":"Permits action"},{"label":"Affecting input at 0","value":"Imposes 0 state"},{"label":"Artwork scope","value":"Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic"}],"references":[{"sourceId":"s28-ti-ieee91-logic-symbols","relevance":"Section on G (AND) dependency and summary table of dependency notation."}],"related":["iec-or-dependency-v","iec-control-dependency-c","iec-multiplexer"],"artwork":"s28-iec-and-dependency-g","publishedOn":"2026-10-28","updatedOn":"2026-10-28","provenance":"independent-public-research","symbolVariant":{"convention":"IEC","form":"Affecting input labelled Gm with affected inputs or outputs labelled m","reference":"Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier."},"plainEnglish":{"title":"What does IEC AND dependency (G) mean?","introduction":"In dependency notation, an input labelled G followed by a number is an affecting input. Every input or output labelled with the same number is ANDed with it. When the G input is at its internal 1 state the affected signals act normally; at its internal 0 state they are forced to 0. A bar over the number means the complement of the G input affects them.","example":"G dependency lets a device symbol show gating relationships without drawing extra AND gates. It is common on multiplexers, gated clocks and register symbols in device data books, and a drafter copying such a symbol must keep the numbers intact or the meaning changes.","drawings":"The label describes logic only. It does not tell you whether the gating causes glitches on a clock line or what setup time applies between G and the affected input.","terms":[{"name":"Signal","meaning":"Electrical information passed between devices, rather than necessarily the main power supply."},{"name":"Schematic","meaning":"A drawing showing function and connections rather than physical appearance."}],"diagram":"flow","steps":["Identify the device and form","Read the connections and state","Check the equipment reference"],"caption":"A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.","sources":[{"label":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf"}],"detail":"Dependency label Gm: inputs or outputs carrying the number m are ANDed with the affecting G input. V (OR) dependency imposes a 1 state when the affecting input is 1; G imposes a 0 state when the affecting input is 0.","profileId":"reviewed-symbol-20261028"},"url":"https://eloragrid.ai/symbols/iec-and-dependency-g","illustration":{"url":"https://eloragrid.ai/tools/electrical-library/illustrations/iec-and-dependency-g.svg","scope":"Original educational concept; not an official standard graphic or product footprint","license":"https://creativecommons.org/licenses/by/4.0/"},"sources":[{"id":"s28-ti-ieee91-logic-symbols","title":"Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)","publisher":"Texas Instruments","url":"https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf","type":"manufacturer","scope":"Public explanation of rectangular logic symbols, general qualifiers, input and output qualifiers, dependency notation, bistable elements and coders, consistent with IEC 617-12 work.","checkedOn":"2026-10-28","reuse":"link-only","relevance":"Section on G (AND) dependency and summary table of dependency notation."}]}