# IEC AND-OR-invert element

Canonical URL: https://eloragrid.ai/symbols/iec-and-or-invert-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: AOI
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Embedded & elements abutting a ≥1 element with negated output
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.

Two & elements embedded in a ≥1 element with negated output, drawn as one compound IEC AND-OR-invert symbol.

## In plain English

### What does IEC AND-OR-invert element mean?

The IEC system draws an AND-OR-invert as several & elements abutted against the left side of a ≥1 element, whose output is negated. Because the common line between the & and ≥1 parts is perpendicular to the signal flow, each & element is understood to feed one input of the OR.

### A simple example

AOI structures appear in older TTL-based control boards and in some gate-array documentation. On a drawing they compress several gates into one symbol, so the reader should expand the function mentally as the complement of a sum of products before checking a truth table.

### What the drawings help you do

The compound symbol does not show internal timing or whether unused AND inputs are tied. Unused inputs on the physical device must be handled as the datasheet requires.

### This particular reference

Two & elements embedded in a ≥1 element with negated output, drawn as one compound IEC AND-OR-invert symbol. Separate AND gates wired to a NOR gate perform the same function but are drawn as distinct elements with visible interconnections.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74LS51 AND-OR-invert gates](https://www.ti.com/lit/ds/symlink/sn74ls51.pdf)


## What it represents

The IEC system draws an AND-OR-invert as several & elements abutted against the left side of a ≥1 element, whose output is negated. Because the common line between the & and ≥1 parts is perpendicular to the signal flow, each & element is understood to feed one input of the OR.
AOI structures appear in older TTL-based control boards and in some gate-array documentation. On a drawing they compress several gates into one symbol, so the reader should expand the function mentally as the complement of a sum of products before checking a truth table.
The compound symbol does not show internal timing or whether unused AND inputs are tied. Unused inputs on the physical device must be handled as the datasheet requires.

## How to read it

- Read the embedded & elements as product terms feeding the ≥1 element.
- Remember the final negation at the output.

## Information to show or reference

- Abut the & elements cleanly to the ≥1 outline.
- Label every input.
- Show the tie-off for unused inputs.

## Important distinction

Separate AND gates wired to a NOR gate perform the same function but are drawn as distinct elements with visible interconnections.

## Facts

- Structure: & elements embedded in ≥1 with output negation
- Boolean form: NOT((A AND B) OR (C AND D))
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Explains abutted and embedded outlines and their implied connections.
- [SN74LS51 AND-OR-invert gates](https://www.ti.com/lit/ds/symlink/sn74ls51.pdf) — Texas Instruments. Manufacturer AND-OR-invert gate documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.