# IEC clocked SR flip-flop Canonical URL: https://eloragrid.ai/symbols/iec-clocked-sr-flip-flop Publisher: Elora Grid Updated: 2026-10-28 Lookup label: 1S 1R Drawing use: Schematic Reference families: IEC, Manufacturer ## Symbol convention Convention: IEC Form: Rectangular bistable with 1S, 1R and C1 inputs Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. IEC bistable with 1S and 1R inputs that act only under C1 control, giving a synchronous set-reset function. ## In plain English ### What does IEC clocked SR flip-flop mean? Adding the C1 prefix to S and R makes them synchronous: they act only when C1 is active or on its active transition. The element therefore combines set-reset storage with clocking, which keeps state changes aligned with the rest of a synchronous system. ### A simple example Clocked SR elements appear in function-block diagrams for PLCs and in state-machine documentation. On hardware schematics the same function is often implemented with a JK or D flip-flop and gating, so cross-reference the implementation. ### What the drawings help you do The symbol needs a stated rule for 1S and 1R active together. Without S or R dependency or a note, that condition is undefined. ### This particular reference IEC bistable with 1S and 1R inputs that act only under C1 control, giving a synchronous set-reset function. The unclocked IEC SR latch acts immediately on S and R. ### Terms - Schematic: A drawing showing function and connections rather than physical appearance. Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram. - [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) ## What it represents Adding the C1 prefix to S and R makes them synchronous: they act only when C1 is active or on its active transition. The element therefore combines set-reset storage with clocking, which keeps state changes aligned with the rest of a synchronous system. Clocked SR elements appear in function-block diagrams for PLCs and in state-machine documentation. On hardware schematics the same function is often implemented with a JK or D flip-flop and gating, so cross-reference the implementation. The symbol needs a stated rule for 1S and 1R active together. Without S or R dependency or a note, that condition is undefined. ## How to read it - Prefix numbers on S and R show they are synchronous. - Look for a priority statement for both inputs active. ## Information to show or reference - Label 1S and 1R inside the outline. - Mark C1 dynamic if edge-triggered. - State set or reset priority. ## Important distinction The unclocked IEC SR latch acts immediately on S and R. ## Facts - Key labels: 1S, 1R, C1 - Behaviour: Synchronous set and reset - Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic ## Public references - [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. C dependency applied to S and R inputs on bistable elements. ## Graphic scope Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.