# IEC D flip-flop (rectangular form)

Canonical URL: https://eloragrid.ai/symbols/iec-d-flip-flop
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: 1D
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Rectangular bistable with dynamic C1 input and 1D data input
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [Positive-edge D flip-flop](https://eloragrid.ai/symbols/positive-edge-d-flip-flop)

IEC bistable with a dynamic C1 clock and a 1D data input, storing D on the active clock edge.

## In plain English

### What does IEC D flip-flop (rectangular form) mean?

In IEC form the D flip-flop is an unlabelled bistable outline with a clock input labelled C1 carrying the dynamic wedge, and a data input labelled 1D to show it is controlled by C1. Asynchronous set and reset inputs are labelled S and R without a number. The two outputs are Q and its complement shown with a negation or polarity mark.

### A simple example

TI's overview stresses that a D input always sets the storage element to 1 at its internal 1 state and resets it at 0. On sequential drawings this form makes clocking explicit: anything without the 1 prefix acts immediately, regardless of the clock.

### What the drawings help you do

The symbol does not state setup, hold or travel times, and does not define the power-up state unless an I=0 or I=1 additional drawing mark is added.

### This particular reference

IEC bistable with a dynamic C1 clock and a 1D data input, storing D on the active clock edge. The IEC D latch has a C1 input without a dynamic mark and is transparent while C1 is active.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC74 — positive-edge D flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf)


## What it represents

In IEC form the D flip-flop is an unlabelled bistable outline with a clock input labelled C1 carrying the dynamic wedge, and a data input labelled 1D to show it is controlled by C1. Asynchronous set and reset inputs are labelled S and R without a number. The two outputs are Q and its complement shown with a negation or polarity mark.
TI's overview stresses that a D input always sets the storage element to 1 at its internal 1 state and resets it at 0. On sequential drawings this form makes clocking explicit: anything without the 1 prefix acts immediately, regardless of the clock.
The symbol does not state setup, hold or propagation times, and does not define the power-up state unless an I=0 or I=1 qualifier is added.

## How to read it

- The wedge on C1 indicates edge triggering.
- S and R without numbers are asynchronous.

## Information to show or reference

- Label the clock C1 with a dynamic mark.
- Prefix the data input with 1.
- Add I=0 or I=1 where power-up state matters.

## Important distinction

The IEC D latch has a C1 input without a dynamic mark and is transparent while C1 is active.

## Facts

- Key labels: C1 (dynamic), 1D, S, R
- Outputs: Q and complemented Q
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Bistable element forms and C dependency with D inputs.
- [SN74HC74 — positive-edge D flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf) — Texas Instruments. D flip-flop device documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.