# IEC dynamic input (edge-triggered)

Canonical URL: https://eloragrid.ai/symbols/iec-dynamic-input
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: DYN
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Small wedge inside the outline at the input
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.

Wedge drawn inside the outline at an input, meaning the input acts on a transition rather than a level.

## In plain English

### What does IEC dynamic input (edge-triggered) mean?

The dynamic input indicator is a small wedge inside the outline at the point where the input line enters. It means the input is active only on a transition, normally from external 0 to 1 in positive logic. It is the mark that distinguishes an edge-triggered flip-flop clock from a level-sensitive latch enable.

### A simple example

On sequential logic drawings the reader should look for the wedge at every C input. A missing wedge on a clock input changes the device from edge-triggered to transparent, which changes timing behaviour significantly.

### What the drawings help you do

The wedge does not specify setup or hold time, nor maximum clock rate. Those are device timing parameters. Check the active clock edge against the input waveform and the timing data of the actual logic element.

### This particular reference

Wedge drawn inside the outline at an input, meaning the input acts on a transition rather than a level. The postponed-output mark relates to pulse-triggered elements whose output changes at the end of the pulse, not at the edge.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC74 — positive-edge D flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf)


## What it represents

The dynamic input indicator is a small wedge inside the outline at the point where the input line enters. It means the input is active only on a transition, normally from external 0 to 1 in positive logic. It is the mark that distinguishes an edge-triggered flip-flop clock from a level-sensitive latch enable.
On sequential logic drawings the reader should look for the wedge at every C input. A missing wedge on a clock input changes the device from edge-triggered to transparent, which changes timing behaviour significantly.
The wedge does not specify setup or hold time, nor maximum clock rate. Those are device timing parameters. Check the active clock edge against the input waveform and the timing data of the actual logic element.

## How to read it

- Wedge present: edge-triggered; wedge absent: level-sensitive.
- Check for a negation or polarity mark that reverses the active edge.

## Information to show or reference

- Draw the wedge inside the outline at the clock input.
- Show negation outside the outline for falling-edge inputs.
- Label the input with its dependency number, for example C1.

## Important distinction

The postponed-output mark relates to pulse-triggered elements whose output changes at the end of the pulse, not at the edge.

## Facts

- Meaning: Active on a transition
- Typical label: C1 on a clock input
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Dynamic input indication in positive logic, negative logic and polarity notation.
- [SN74HC74 — positive-edge D flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf) — Texas Instruments. Edge-triggered flip-flop documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.