# IEC first-in first-out memory (FIFO) Canonical URL: https://eloragrid.ai/symbols/iec-fifo-memory Publisher: Elora Grid Updated: 2026-10-28 Lookup label: FIFO Drawing use: Schematic Reference families: IEC, Manufacturer ## Symbol convention Convention: IEC Form: Rectangular element with FIFO qualifier, write and read clocks and status outputs Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. IEC element marked FIFO that stores words in arrival order and reads them out in the same order. ## In plain English ### What does IEC first-in first-out memory (FIFO) mean? The FIFO additional drawing mark identifies a first-in first-out memory. There are no address inputs; instead, a write clock stores input words and a read clock delivers them in the same order. Status outputs indicate empty, full and sometimes half-full conditions. ### A simple example FIFOs buffer data between parts of a system that run at different rates, such as a serial receiver and a processor. On a drawing, the status outputs should be traced to see how the system avoids overflow and underflow. ### What the drawings help you do The symbol does not specify depth or whether read and write clocks can be asynchronous. The organisation and device data provide those details. ### This particular reference IEC element marked FIFO that stores words in arrival order and reads them out in the same order. RAM uses addresses; FIFO uses order of arrival. ### Terms - Normally open / normally closed: The contact state in the normal condition defined for the drawing. - Signal: Electrical information passed between devices, rather than necessarily the main power supply. - Schematic: A drawing showing function and connections rather than physical appearance. Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram. - [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) ## What it represents The FIFO qualifier identifies a first-in first-out memory. There are no address inputs; instead, a write clock stores input words and a read clock delivers them in the same order. Status outputs indicate empty, full and sometimes half-full conditions. FIFOs buffer data between parts of a system that run at different rates, such as a serial receiver and a processor. On a drawing, the status outputs should be traced to see how the system avoids overflow and underflow. The symbol does not specify depth or whether read and write clocks can be asynchronous. The organisation and device data provide those details. ## How to read it - No address inputs: order is implicit. - Trace full and empty flags to their handling logic. ## Information to show or reference - State depth and width. - Label write and read clocks. - Show status outputs and their use. ## Important distinction RAM uses addresses; FIFO uses order of arrival. ## Facts - Qualifier: FIFO - Status outputs: Empty, full, often half-full - Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic ## Public references - [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Lists FIFO as a general qualifier. ## Graphic scope Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.