# IEC JK flip-flop (rectangular form)

Canonical URL: https://eloragrid.ai/symbols/iec-jk-flip-flop
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: 1J 1K
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Rectangular bistable with 1J, 1K and dynamic C1 inputs
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [Negative-edge JK flip-flop](https://eloragrid.ai/symbols/negative-edge-jk-flip-flop)

IEC bistable with 1J and 1K inputs controlled by a dynamic C1 clock; J=K=1 toggles the state.

## In plain English

### What does IEC JK flip-flop (rectangular form) mean?

The IEC JK flip-flop has inputs labelled 1J and 1K, both controlled by C1. On the active clock transition J=1, K=0 sets; J=0, K=1 resets; J=K=1 toggles; and J=K=0 holds. A negation mark outside the C1 input with the wedge indicates a falling-edge device.

### A simple example

JK devices are used in counters and divider chains. On IEC drawings check the clock marking carefully, because rising-edge and falling-edge versions are visually similar and mixing them changes counter sequencing.

### What the drawings help you do

The rectangle does not reveal whether the device is edge-triggered or pulse-triggered unless the clock and output marks are read together. A postponed output mark indicates a pulse-triggered type.

### This particular reference

IEC bistable with 1J and 1K inputs controlled by a dynamic C1 clock; J=K=1 toggles the state. An IEC T flip-flop has a single 1T input; a JK with J and K tied high behaves the same way.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC112 — negative-edge JK flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc112.pdf)


## What it represents

The IEC JK flip-flop has inputs labelled 1J and 1K, both controlled by C1. On the active clock transition J=1, K=0 sets; J=0, K=1 resets; J=K=1 toggles; and J=K=0 holds. A negation mark outside the C1 input with the wedge indicates a falling-edge device.
JK devices are used in counters and divider chains. On IEC drawings check the clock marking carefully, because rising-edge and falling-edge versions are visually similar and mixing them changes counter sequencing.
The rectangle does not reveal whether the device is edge-triggered or pulse-triggered unless the clock and output marks are read together. A postponed output mark indicates a pulse-triggered type.

## How to read it

- Read the clock edge from the wedge and any external negation.
- Look for postponed output marks.

## Information to show or reference

- Label J and K with the C prefix.
- Show the active clock edge clearly.
- Show asynchronous S and R inputs where present.

## Important distinction

An IEC T flip-flop has a single 1T input; a JK with J and K tied high behaves the same way.

## Facts

- Key labels: 1J, 1K, C1
- J=K=1: Toggle on active edge
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Bistable element types and J, K label meanings.
- [SN74HC112 — negative-edge JK flip-flops](https://www.ti.com/lit/ds/symlink/sn74hc112.pdf) — Texas Instruments. Negative-edge JK flip-flop documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.