# IEC OR gate (rectangular form)

Canonical URL: https://eloragrid.ai/symbols/iec-or-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: ≥1
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Rectangular outline with the ≥1 general qualifying symbol
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [OR gate](https://eloragrid.ai/symbols/logic-or-gate)

IEC rectangular OR element labelled ≥1, meaning at least one active input is needed to activate the output.

## In plain English

### What does IEC OR gate (rectangular form) mean?

The ≥1 additional drawing mark inside a rectangular outline identifies an OR function. The notation literally reads as at least one input active, which is why the same family of symbols uses ≥m for threshold functions in other contexts. Inputs are drawn on the left and the output on the right unless an arrow indicates otherwise.

### A simple example

On trip logic and permissive diagrams the ≥1 box often collects several fault signals into a single trip command. Because every input is equal, the drawing should label each incoming signal with its source tag so that a reader can trace which condition caused the output during testing.

### What the drawings help you do

The symbol does not state whether the inputs are latched, filtered or time-delayed. Any such behaviour must be shown by separate elements or by labels; the OR box itself is purely combinative.

### This particular reference

IEC rectangular OR element labelled ≥1, meaning at least one active input is needed to activate the output. A box marked 1 alone is a buffer or single-input element; ≥1 is required for the OR function.

### Terms

- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC32 — OR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc32.pdf)


## What it represents

The ≥1 qualifier inside a rectangular outline identifies an OR function. The notation literally reads as at least one input active, which is why the same family of symbols uses ≥m for threshold functions in other contexts. Inputs are drawn on the left and the output on the right unless an arrow indicates otherwise.
On trip logic and permissive diagrams the ≥1 box often collects several fault signals into a single trip command. Because every input is equal, the drawing should label each incoming signal with its source tag so that a reader can trace which condition caused the output during testing.
The symbol does not state whether the inputs are latched, filtered or time-delayed. Any such behaviour must be shown by separate elements or by labels; the OR box itself is purely combinative.

## How to read it

- Trace each input back to its source tag; the box does not identify which input fired.
- A circle at the output turns the element into a NOR function.

## Information to show or reference

- Write ≥1 legibly; do not abbreviate to 1, which is the buffer qualifier.
- Label each input signal with its source.
- Show negation at inputs or output explicitly.

## Important distinction

A box marked 1 alone is a buffer or single-input element; ≥1 is required for the OR function.

## Facts

- General qualifier: ≥1 (at least one input active)
- Typical use: Collecting several trip or alarm conditions
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Defines ≥1 as the OR qualifier and explains why it was chosen.
- [SN74HC32 — OR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc32.pdf) — Texas Instruments. Manufacturer OR gate documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.