# IEC exclusive-OR gate (rectangular form)

Canonical URL: https://eloragrid.ai/symbols/iec-xor-gate
Publisher: Elora Grid
Updated: 2026-10-28
Lookup label: =1
Drawing use: Schematic
Reference families: IEC, Manufacturer

## Symbol convention

Convention: IEC
Form: Rectangular outline with the =1 qualifier
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Related representation: [Exclusive-OR gate](https://eloragrid.ai/symbols/logic-xor-gate)

Rectangular element marked =1: the output is active when one and only one input is active.

## In plain English

### What does IEC exclusive-OR gate (rectangular form) mean?

The =1 additional drawing mark defines an exclusive-OR in the strict IEC sense: exactly one input must be active for the output to be active. For a two-input element this matches the familiar XOR truth table. For more than two inputs it is not the same as a cascaded parity function, which IEC writes as 2k+1.

### A simple example

On control drawings the =1 element appears in discrepancy checks, such as comparing a commanded position with a feedback contact, and in change-detection logic. The drafter should keep the element at two inputs unless the one-and-only-one meaning is truly intended.

### What the drawings help you do

The additional drawing mark does not indicate timing tolerance. Discrepancy logic normally needs a delay element after the =1 box so that the alarm ignores normal transit time; that delay is a separate symbol.

### This particular reference

Rectangular element marked =1: the output is active when one and only one input is active. The 2k+1 odd-parity element gives the same result for two inputs but a different result for three or more.

### Terms

- Normally open / normally closed: The contact state in the normal condition defined for the drawing.
- Signal: Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic: A drawing showing function and connections rather than physical appearance.

Concept diagram: Identify the device and form → Read the connections and state → Check the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf)
- [SN74HC86 — XOR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc86.pdf)


## What it represents

The =1 qualifier defines an exclusive-OR in the strict IEC sense: exactly one input must be active for the output to be active. For a two-input element this matches the familiar XOR truth table. For more than two inputs it is not the same as a cascaded parity function, which IEC writes as 2k+1.
On control drawings the =1 element appears in discrepancy checks, such as comparing a commanded position with a feedback contact, and in change-detection logic. The drafter should keep the element at two inputs unless the one-and-only-one meaning is truly intended.
The qualifier does not indicate timing tolerance. Discrepancy logic normally needs a delay element after the =1 box so that the alarm ignores normal transit time; that delay is a separate symbol.

## How to read it

- For three or more inputs, read =1 as exactly one active, not odd parity.
- Look for a following delay element in discrepancy logic.

## Information to show or reference

- Use =1 only where exactly-one behaviour is intended.
- Use 2k+1 instead when odd parity is meant.
- Show any discrepancy delay as its own element.

## Important distinction

The 2k+1 odd-parity element gives the same result for two inputs but a different result for three or more.

## Facts

- Qualifier: =1 (one and only one input active)
- Multi-input caution: Not equivalent to odd parity above two inputs
- Artwork scope: Original educational illustration; consult the applicable standard and the selected device documentation for the exact graphic

## Public references

- [Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)](https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf) — Texas Instruments. Defines =1 and distinguishes it from the 2k+1 parity qualifier.
- [SN74HC86 — XOR gate logic](https://www.ti.com/lit/ds/symlink/sn74hc86.pdf) — Texas Instruments. Manufacturer exclusive-OR documentation.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.