# LVDS line receiver

Canonical URL: https://eloragrid.ai/symbols/lvds-line-receiver
Publisher: Elora Grid
Updated: 2026-10-27
Lookup label: LVDS RX
Drawing use: Schematic
Reference families: Manufacturer

An LVDS receiver converts a compatible differential input into its specified logic output.

## In plain English

### What does LVDS line receiver mean?

An LVDS receiver converts a compatible differential input into its specified logic output.

### A simple example

The receiving end of a link can recover the logic state from the differential pair.

### What the drawings help you do

Identify the differential input pair and the receiver’s logic output. The pair’s valid input conditions and the output’s logic levels are separate specifications. Keep the sender and receiver labels visible so the drawing describes a complete direction of information flow.

### Before using this reference

- Label the differential input pair consistently with the driver.
- Reference accepted input conditions and termination.
- Identify the output logic supply and destination.

### Are the input pair and output at the same electrical levels?

Not necessarily. The receiver converts the selected differential input into its specified logic output. Both sides’ electrical requirements must be checked for the actual device.

### Terms

- Differential input: A signal interpreted from the difference between its two conductors.
- Logic output: The electrical signal presented to the receiving digital circuit.

Concept diagram: Differential input pair → LVDS line receiver → Logic output signal
Original functional explanation. Arrows show information or energy roles; two-headed arrows identify two-way interfaces. This is not a pinout, certified standards graphic or complete circuit.

- [Low-voltage differential signalling](https://www.ti.com/product-category/interface/lvds-m-lvds-pecl-ics/overview.html)


## What it represents

An LVDS receiver converts a compatible differential input into its specified logic output.
The receiving end of a link can recover the logic state from the differential pair.
Identify the differential input pair and the receiver’s logic output. The pair’s valid input conditions and the output’s logic levels are separate specifications. Keep the sender and receiver labels visible so the drawing describes a complete direction of information flow. This is original functional artwork, not a certified standard graphic or device pinout.

## How to read it

- Label the differential input pair consistently with the driver.
- Reference accepted input conditions and termination.
- Identify the output logic supply and destination.
- A receiver's accepted input conditions and output logic levels are separate specifications.

## Information to show or reference

- Label the differential input pair consistently with the driver.
- Reference accepted input conditions and termination.
- Identify the output logic supply and destination.

## Important distinction

A receiver's accepted input conditions and output logic levels are separate specifications.

## Facts

- Representation type: Original functional block; not a certified IEC or IEEE graphic
- Concept input: Differential input pair
- Concept output: Logic output signal

## Public references

- [Low-voltage differential signalling](https://www.ti.com/product-category/interface/lvds-m-lvds-pecl-ics/overview.html) — Texas Instruments. Low-voltage differential signalling: public technical context for the named function. Product and compliance details remain with the publisher.

## Graphic scope

Independent original educational concept illustration by Elora Grid. Not a certified standards graphic or manufacturer footprint. Unitless; not to scale. Original artwork licence: https://creativecommons.org/licenses/by/4.0/. Publisher material is linked only.