NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic
IEEE / ANSI · NAND-ST
ANSI Schmitt-trigger NAND gate
NAND outline with a hysteresis mark inside, combining the NAND function with Schmitt-trigger inputs.
In plain English
What does ANSI Schmitt-trigger NAND gate mean?
A Schmitt-trigger NAND is drawn as a normal NAND outline with the hysteresis mark inside the body. Each input switches at different rising and falling thresholds, so the gate accepts slow or noisy signals while still performing the NAND function.
A simple example
These gates are often used for gated oscillators, where one input enables an RC oscillator built around the gate, and for combining a debounced contact with an enable signal. Timing components should be drawn close to the gate with the intended frequency or delay noted.
What the drawings help you do
Threshold levels and hysteresis width are not shown by the symbol and differ between logic families. Read them from the device documentation.
This particular reference
NAND outline with a hysteresis mark inside, combining the NAND function with Schmitt-trigger inputs. A standard NAND has no hysteresis mark and a single threshold.
- Normally open / normally closed
- The contact state in the normal condition defined for the drawing.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: SNx4HC132 quadruple 2-input NAND gates with Schmitt-trigger inputs
IEEE / ANSI · NAND outline containing the hysteresis mark
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · NAND-ST
What it represents
A Schmitt-trigger NAND is drawn as a normal NAND outline with the hysteresis mark inside the body. Each input switches at different rising and falling thresholds, so the gate accepts slow or noisy signals while still performing the NAND function.
These gates are often used for gated oscillators, where one input enables an RC oscillator built around the gate, and for combining a debounced contact with an enable signal. Timing components should be drawn close to the gate with the intended frequency or delay noted.
Threshold levels and hysteresis width are not shown by the symbol and differ between logic families. Read them from the device documentation.
How to read it
- Spot the hysteresis mark inside the NAND body.
- Check for RC components that create an oscillator.
Information to show or reference
- Show the hysteresis mark within the outline.
- Keep timing components adjacent.
- State the intended oscillator frequency or debounce time.
A distinction that matters
A standard NAND has no hysteresis mark and a single threshold.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SNx4HC132 quadruple 2-input NAND gates with Schmitt-trigger inputs
Manufacturer documentation for NAND gates with Schmitt-trigger inputs.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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