AND
AND gate
A logic element whose output is true when all stated positive-logic inputs are true.
Schematic
Symbols · NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic · NAND
What it represents
A logic gate that inverts the result of an AND operation.
On a schematic, identify the input truth states and the output inversion indication and trace the output logic state and downstream input. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
The inversion bubble concerns logical polarity; it does not identify a normally-closed physical contact.
Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.
How to read it
- Identify the input truth states and the output inversion indication.
- Trace the output logic state and downstream input.
Information to show or reference
- Label the input truth states and the output inversion indication.
- Cross-reference the output logic state and downstream input.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
The inversion bubble concerns logical polarity; it does not identify a normally-closed physical contact.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC00 — NAND gate logic
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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