ADD
Binary full adder
Adds binary input words with the documented carry-in and produces sum and carry outputs.
Schematic
IEC · Σ
IEC adder (Σ)
IEC element marked Σ that adds binary words P and Q with carry-in CI and carry-out CO.
In plain English
What does IEC adder (Σ) mean?
The adder additional drawing mark is the capital sigma. Inputs are grouped into P and Q words with binary weights, plus a carry input CI; outputs give the sum with weights and a carry output CO. TI's overview lists Σ alongside P-Q for subtraction and CPG for look-ahead carry generation.
A simple example
Adders on drawings usually belong to arithmetic sections of logic boards, counters with preset arithmetic, or illustrations of PLC arithmetic blocks. The carry chain between stages should be drawn so that the word length is obvious.
What the drawings help you do
The symbol does not state whether the device uses ripple or look-ahead carry internally. Speed depends on that and on the word length.
This particular reference
IEC element marked Σ that adds binary words P and Q with carry-in CI and carry-out CO. A subtracter carries the P-Q additional drawing mark instead; Σ marks an adder.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · CD74HC283 — binary full adders
IEC · Rectangular element with Σ qualifier, P and Q inputs, CI and CO
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · Σ
What it represents
The adder qualifier is the capital sigma. Inputs are grouped into P and Q words with binary weights, plus a carry input CI; outputs give the sum with weights and a carry output CO. TI's overview lists Σ alongside P-Q for subtraction and CPG for look-ahead carry generation.
Adders on drawings usually belong to arithmetic sections of logic boards, counters with preset arithmetic, or illustrations of PLC arithmetic blocks. The carry chain between stages should be drawn so that the word length is obvious.
The symbol does not state whether the device uses ripple or look-ahead carry internally. Speed depends on that and on the word length.
How to read it
- Check carry-in and carry-out connections between stages.
- Bit weights define the word order.
Information to show or reference
- Mark the element with Σ.
- Label P, Q, CI and CO.
- Show the carry chain for multi-device words.
A distinction that matters
A subtracter carries the P-Q qualifier instead; Σ marks an adder.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Lists Σ as the adder qualifier.
CD74HC283 — binary full adders
Binary full adder documentation.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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