IEC OR dependency (V)
Dependency label Vm: affected terminals are ORed with the V input, forced to 1 when V is active.
Dependency label Gm: inputs or outputs carrying the number m are ANDed with the affecting G input.
In plain English
In dependency notation, an input labelled G followed by a number is an affecting input. Every input or output labelled with the same number is ANDed with it. When the G input is at its internal 1 state the affected signals act normally; at its internal 0 state they are forced to 0. A bar over the number means the complement of the G input affects them.
G dependency lets a device symbol show gating relationships without drawing extra AND gates. It is common on multiplexers, gated clocks and register symbols in device data books, and a drafter copying such a symbol must keep the numbers intact or the meaning changes.
The label describes logic only. It does not tell you whether the gating causes glitches on a clock line or what setup time applies between G and the affected input.
Dependency label Gm: inputs or outputs carrying the number m are ANDed with the affecting G input. V (OR) dependency imposes a 1 state when the affecting input is 1; G imposes a 0 state when the affecting input is 0.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.
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In dependency notation, an input labelled G followed by a number is an affecting input. Every input or output labelled with the same number is ANDed with it. When the G input is at its internal 1 state the affected signals act normally; at its internal 0 state they are forced to 0. A bar over the number means the complement of the G input affects them.
G dependency lets a device symbol show gating relationships without drawing extra AND gates. It is common on multiplexers, gated clocks and register symbols in device data books, and a drafter copying such a symbol must keep the numbers intact or the meaning changes.
The label describes logic only. It does not tell you whether the gating causes glitches on a clock line or what setup time applies between G and the affected input.
V (OR) dependency imposes a 1 state when the affecting input is 1; G imposes a 0 state when the affecting input is 0.
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Section on G (AND) dependency and summary table of dependency notation.
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