Gm
IEC AND dependency (G)
Dependency label Gm: inputs or outputs carrying the number m are ANDed with the affecting G input.
IEC
IEC · Vm
IEC OR dependency (V)
Dependency label Vm: affected terminals are ORed with the V input, forced to 1 when V is active.
In plain English
What does IEC OR dependency (V) mean?
V dependency is the OR counterpart of G dependency. When the Vm affecting input is at its internal 1 state, every input or output labelled m is forced to its internal 1 state. When Vm is at 0, the affected signals act normally.
A simple example
Device symbols use V dependency to show override or force functions, for example an output that can be forced active regardless of the normal logic. Recognising the letter avoids misreading the affected output as purely driven by the main function.
What the drawings help you do
Like all dependency labels, V gives no timing information and does not imply a particular circuit. It is a compact statement of a logical relationship within the symbol.
This particular reference
Dependency label Vm: affected terminals are ORed with the V input, forced to 1 when V is active. G dependency is the AND relationship; V is the OR relationship.
- Normally open / normally closed
- The contact state in the normal condition defined for the drawing.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
IEC · Affecting input labelled Vm with affected terminals labelled m
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · Vm
What it represents
V dependency is the OR counterpart of G dependency. When the Vm affecting input is at its internal 1 state, every input or output labelled m is forced to its internal 1 state. When Vm is at 0, the affected signals act normally.
Device symbols use V dependency to show override or force functions, for example an output that can be forced active regardless of the normal logic. Recognising the letter avoids misreading the affected output as purely driven by the main function.
Like all dependency labels, V gives no timing information and does not imply a particular circuit. It is a compact statement of a logical relationship within the symbol.
How to read it
- V forces affected terminals to 1; G forces them to 0.
- Look for a bar over the number for complemented action.
Information to show or reference
- Label the affecting input with V and a number.
- Mark every affected terminal with the same number.
- Explain any override behaviour in the sheet notes.
A distinction that matters
G dependency is the AND relationship; V is the OR relationship.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
V (OR) dependency description and summary table.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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