IEC · DYN-NEG

IEC dynamic input with negation (falling edge)

Clock wedge combined with a negation circle or polarity triangle, so the input acts on a falling edge.

In plain English

What does IEC dynamic input with negation (falling edge) mean?

Combining the dynamic input wedge with input negation, or with a polarity indicator, means the input is active on the transition from high to low. TI's public overview tabulates how the active transition reads in positive logic, negative logic and polarity notation.

A simple example

Negative-edge clocking appears in JK flip-flops and some counters, and in designs where two stages are clocked on opposite edges. A reader must check both the wedge and the external mark before deciding which edge the device responds to.

Identify the device and formRead the connections and stateCheck the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

What the drawings help you do

The symbol does not state duty-cycle or minimum pulse width requirements; those come from device timing data. The input waveform must satisfy those limits at the active falling transition, not just reach a valid steady logic level.

This particular reference

Clock wedge combined with a negation circle or polarity triangle, so the input acts on a falling edge. A wedge without an external mark is rising-edge triggered.

Signal
Electrical information passed between devices, rather than necessarily the main power supply.
Schematic
A drawing showing function and connections rather than physical appearance.

Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC112 — negative-edge JK flip-flops

IEC · Wedge inside the outline combined with an external negation circle or polarity triangle

Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.

Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.

Schematic · DYN-NEGIEC dynamic input with negation (falling edge): original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

Combining the dynamic input wedge with input negation, or with a polarity indicator, means the input is active on the transition from high to low. TI's public overview tabulates how the active transition reads in positive logic, negative logic and polarity notation.

Negative-edge clocking appears in JK flip-flops and some counters, and in designs where two stages are clocked on opposite edges. A reader must check both the wedge and the external mark before deciding which edge the device responds to.

The symbol does not state duty-cycle or minimum pulse width requirements; those come from device timing data. The input waveform must satisfy those limits at the active falling transition, not just reach a valid steady logic level.

How to read it

  • Look outside the outline for the circle or triangle as well as inside for the wedge.
  • Opposite-edge clocking between stages is often deliberate.

Information to show or reference

  • Draw both the wedge and the external negation mark.
  • Keep notation consistent with the rest of the sheet.
  • Annotate the clock net with its active edge if mixed edges are used.

A distinction that matters

A wedge without an external mark is rising-edge triggered.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

Tabulates dynamic input forms for each logic convention.

Texas Instruments · Public reference checked 28 October 2026 · Link only

SN74HC112 — negative-edge JK flip-flops

Negative-edge JK flip-flop documentation.

Texas Instruments · Public reference checked 14 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 28 October 2026

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