JK-FF
Negative-edge JK flip-flop
Updates or toggles its stored state from J and K inputs at the selected negative clock edge.
Schematic
IEC · 1J 1K
IEC JK flip-flop (rectangular form)
IEC bistable with 1J and 1K inputs controlled by a dynamic C1 clock; J=K=1 toggles the state.
In plain English
What does IEC JK flip-flop (rectangular form) mean?
The IEC JK flip-flop has inputs labelled 1J and 1K, both controlled by C1. On the active clock transition J=1, K=0 sets; J=0, K=1 resets; J=K=1 toggles; and J=K=0 holds. A negation mark outside the C1 input with the wedge indicates a falling-edge device.
A simple example
JK devices are used in counters and divider chains. On IEC drawings check the clock marking carefully, because rising-edge and falling-edge versions are visually similar and mixing them changes counter sequencing.
What the drawings help you do
The rectangle does not reveal whether the device is edge-triggered or pulse-triggered unless the clock and output marks are read together. A postponed output mark indicates a pulse-triggered type.
This particular reference
IEC bistable with 1J and 1K inputs controlled by a dynamic C1 clock; J=K=1 toggles the state. An IEC T flip-flop has a single 1T input; a JK with J and K tied high behaves the same way.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC112 — negative-edge JK flip-flops
IEC · Rectangular bistable with 1J, 1K and dynamic C1 inputs
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · 1J 1K
What it represents
The IEC JK flip-flop has inputs labelled 1J and 1K, both controlled by C1. On the active clock transition J=1, K=0 sets; J=0, K=1 resets; J=K=1 toggles; and J=K=0 holds. A negation mark outside the C1 input with the wedge indicates a falling-edge device.
JK devices are used in counters and divider chains. On IEC drawings check the clock marking carefully, because rising-edge and falling-edge versions are visually similar and mixing them changes counter sequencing.
The rectangle does not reveal whether the device is edge-triggered or pulse-triggered unless the clock and output marks are read together. A postponed output mark indicates a pulse-triggered type.
How to read it
- Read the clock edge from the wedge and any external negation.
- Look for postponed output marks.
Information to show or reference
- Label J and K with the C prefix.
- Show the active clock edge clearly.
- Show asynchronous S and R inputs where present.
A distinction that matters
An IEC T flip-flop has a single 1T input; a JK with J and K tied high behaves the same way.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Bistable element types and J, K label meanings.
SN74HC112 — negative-edge JK flip-flops
Negative-edge JK flip-flop documentation.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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