1J 1K
IEC JK flip-flop (rectangular form)
IEC bistable with 1J and 1K inputs controlled by a dynamic C1 clock; J=K=1 toggles the state.
IEC
IEC · 1T
IEC T (toggle) flip-flop
IEC bistable with a 1T toggle input; when T is active, each clock edge changes the stored state.
In plain English
What does IEC T (toggle) flip-flop mean?
The toggle input T causes the internal state to change to its complement. In IEC form it is labelled 1T when controlled by a C1 clock, or drawn as a single dynamic T input where each transition toggles. A T stage is the basic divide-by-two element in counters and frequency dividers.
A simple example
Dedicated T flip-flop packages are rare; the function is usually built from a JK with J and K tied high or a D flip-flop with its complemented output fed back. Functional logic drawings, PLC function-block diagrams and FPGA documentation still use the T form because it states the intent clearly.
What the drawings help you do
The symbol does not show how the toggle function is implemented. Where a JK or D device is used, the physical wiring should appear on the detailed schematic.
This particular reference
IEC bistable with a 1T toggle input; when T is active, each clock edge changes the stored state. A JK flip-flop provides set, reset, hold and toggle; a T element provides only hold and toggle.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
IEC · Rectangular bistable with 1T and dynamic C1 inputs
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · 1T
What it represents
The toggle input T causes the internal state to change to its complement. In IEC form it is labelled 1T when controlled by a C1 clock, or drawn as a single dynamic T input where each transition toggles. A T stage is the basic divide-by-two element in counters and frequency dividers.
Dedicated T flip-flop packages are rare; the function is usually built from a JK with J and K tied high or a D flip-flop with its complemented output fed back. Functional logic drawings, PLC function-block diagrams and FPGA documentation still use the T form because it states the intent clearly.
The symbol does not show how the toggle function is implemented. Where a JK or D device is used, the physical wiring should appear on the detailed schematic.
How to read it
- Read T as change state on each enabled clock.
- Check the implementation on the detailed schematic.
Information to show or reference
- Label the toggle input as 1T with a C1 clock, or as a dynamic T.
- Show initial state where required.
- Cross-reference the implementing JK or D device.
A distinction that matters
A JK flip-flop provides set, reset, hold and toggle; a T element provides only hold and toggle.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Defines the T toggle input.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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