D-LATCH
Transparent D latch
Follows the input data while its latch-enable condition is active and retains it when that condition ends.
Schematic
Symbols · D-FF
Positive-edge D flip-flop
Captures its data input at the documented positive clock edge and retains that digital state.
Schematic · D-FF
What it represents
Captures its data input at the documented positive clock edge and retains that digital state.
On a schematic, identify the D input, clock edge and asynchronous preset/clear polarities and trace the stored Q output and any complemented output. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
An edge-triggered flip-flop differs from a transparent latch; data timing relative to the clock remains essential.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the D input, clock edge and asynchronous preset/clear polarities.
- Trace the stored Q output and any complemented output.
Information to show or reference
- Label the D input, clock edge and asynchronous preset/clear polarities.
- Cross-reference the stored Q output and any complemented output.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
An edge-triggered flip-flop differs from a transparent latch; data timing relative to the clock remains essential.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC74 — positive-edge D flip-flops
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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