IEC · =1

IEC exclusive-OR gate (rectangular form)

Rectangular element marked =1: the output is active when one and only one input is active.

In plain English

What does IEC exclusive-OR gate (rectangular form) mean?

The =1 additional drawing mark defines an exclusive-OR in the strict IEC sense: exactly one input must be active for the output to be active. For a two-input element this matches the familiar XOR truth table. For more than two inputs it is not the same as a cascaded parity function, which IEC writes as 2k+1.

A simple example

On control drawings the =1 element appears in discrepancy checks, such as comparing a commanded position with a feedback contact, and in change-detection logic. The drafter should keep the element at two inputs unless the one-and-only-one meaning is truly intended.

Identify the device and formRead the connections and stateCheck the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

What the drawings help you do

The additional drawing mark does not indicate timing tolerance. Discrepancy logic normally needs a delay element after the =1 box so that the alarm ignores normal transit time; that delay is a separate symbol.

This particular reference

Rectangular element marked =1: the output is active when one and only one input is active. The 2k+1 odd-parity element gives the same result for two inputs but a different result for three or more.

Normally open / normally closed
The contact state in the normal condition defined for the drawing.
Signal
Electrical information passed between devices, rather than necessarily the main power supply.
Schematic
A drawing showing function and connections rather than physical appearance.

Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC86 — XOR gate logic

IEC · Rectangular outline with the =1 qualifier

Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.

Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.

Schematic · =1IEC exclusive-OR gate (rectangular form): original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

The =1 qualifier defines an exclusive-OR in the strict IEC sense: exactly one input must be active for the output to be active. For a two-input element this matches the familiar XOR truth table. For more than two inputs it is not the same as a cascaded parity function, which IEC writes as 2k+1.

On control drawings the =1 element appears in discrepancy checks, such as comparing a commanded position with a feedback contact, and in change-detection logic. The drafter should keep the element at two inputs unless the one-and-only-one meaning is truly intended.

The qualifier does not indicate timing tolerance. Discrepancy logic normally needs a delay element after the =1 box so that the alarm ignores normal transit time; that delay is a separate symbol.

How to read it

  • For three or more inputs, read =1 as exactly one active, not odd parity.
  • Look for a following delay element in discrepancy logic.

Information to show or reference

  • Use =1 only where exactly-one behaviour is intended.
  • Use 2k+1 instead when odd parity is meant.
  • Show any discrepancy delay as its own element.

A distinction that matters

The 2k+1 odd-parity element gives the same result for two inputs but a different result for three or more.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

Defines =1 and distinguishes it from the 2k+1 parity qualifier.

Texas Instruments · Public reference checked 28 October 2026 · Link only

SN74HC86 — XOR gate logic

Manufacturer exclusive-OR documentation.

Texas Instruments · Public reference checked 14 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 28 October 2026

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