NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic
IEEE / ANSI · NAND4
ANSI four-input NAND gate
Four-input D-shaped NAND gate with an output bubble; its output goes low only when all four inputs are high.
In plain English
What does ANSI four-input NAND gate mean?
A four-input NAND gate is drawn with the AND outline, four input leads and a bubble at the output. The output is low only when every input is high. The function is supplied by dual four-input NAND packages and is a common building block for address decoding and multi-condition alarms.
A simple example
Where some inputs are active low in the design intent, the drawing may show the same device in its De Morgan form as an OR outline with bubbled inputs. Either representation is valid, but the chosen form should match the meaning of the signals so that the sheet reads naturally.
What the drawings help you do
The symbol alone does not show which package or gate section is used. Reference designators and pin numbers come from the device schedule.
This particular reference
Four-input D-shaped NAND gate with an output bubble; its output goes low only when all four inputs are high. An OR outline with bubbled inputs is the De Morgan equivalent of the same NAND function.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: SNx4HC20 dual 4-input NAND gates
IEEE / ANSI · D-shaped AND outline with four inputs and an output bubble
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · NAND4
What it represents
A four-input NAND gate is drawn with the AND outline, four input leads and a bubble at the output. The output is low only when every input is high. The function is supplied by dual four-input NAND packages and is a common building block for address decoding and multi-condition alarms.
Where some inputs are active low in the design intent, the drawing may show the same device in its De Morgan form as an OR outline with bubbled inputs. Either representation is valid, but the chosen form should match the meaning of the signals so that the sheet reads naturally.
The symbol alone does not show which package or gate section is used. Reference designators and pin numbers come from the device schedule.
How to read it
- Check for the output bubble; without it the gate is an AND.
- Consider whether an equivalent OR form is used elsewhere for the same device.
Information to show or reference
- Draw four evenly spaced inputs.
- Mark the output bubble clearly.
- Add the gate section and pin numbers when used for wiring.
A distinction that matters
An OR outline with bubbled inputs is the De Morgan equivalent of the same NAND function.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SNx4HC20 dual 4-input NAND gates
Manufacturer documentation for dual four-input NAND gates.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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