NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic
IEC · &
IEC NAND gate (rectangular form)
IEC AND box with a negation circle or polarity triangle at its output, giving the NAND function.
In plain English
What does IEC NAND gate (rectangular form) mean?
In the IEC rectangular system there is no separate NAND additional drawing mark. The element is an & box whose output carries a logic negation circle, or in data-book practice a polarity triangle marking the output as active-low. The output therefore stands at its external 0 state only when all inputs are active.
A simple example
When reading device data books that use polarity indicators instead of circles, the triangle at the output means the internal 1 state produces a low level. A drawing should be consistent: mixing circles and triangles on the same sheet invites misreading because circles depend on the declared logic convention.
What the drawings help you do
The symbol does not show output drive type. Open-collector, three-state or totem-pole outputs need their own additional drawing mark inside the outline next to the output line.
This particular reference
IEC AND box with a negation circle or polarity triangle at its output, giving the NAND function. An & box with a negated input rather than a negated output is a different function (an inhibit-type AND), not a NAND.
- Normally open / normally closed
- The contact state in the normal condition defined for the drawing.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC00 — NAND gate logic
IEC · & rectangular element with output negation circle
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · &
What it represents
In the IEC rectangular system there is no separate NAND qualifier. The element is an & box whose output carries a logic negation circle, or in data-book practice a polarity triangle marking the output as active-low. The output therefore stands at its external 0 state only when all inputs are active.
When reading device data books that use polarity indicators instead of circles, the triangle at the output means the internal 1 state produces a low level. A drawing should be consistent: mixing circles and triangles on the same sheet invites misreading because circles depend on the declared logic convention.
The symbol does not show output drive type. Open-collector, three-state or totem-pole outputs need their own qualifier inside the outline next to the output line.
How to read it
- Look for the circle or triangle at the output edge; it is easy to miss on a reduced print.
- Confirm whether the sheet uses positive logic, negative logic or polarity indicators.
Information to show or reference
- Draw the negation mark touching the outline at the output.
- State the logic convention in the sheet notes.
- Add an output-type qualifier where the output is not a standard push-pull stage.
A distinction that matters
An & box with a negated input rather than a negated output is a different function (an inhibit-type AND), not a NAND.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Explains output negation and polarity indicator conventions.
SN74HC00 — NAND gate logic
Manufacturer NAND gate documentation.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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