NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic
IEEE / ANSI · NAND
ANSI NAND gate drawn as negative-input OR
OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low.
In plain English
What does ANSI NAND gate drawn as negative-input OR mean?
By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.
A simple example
This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.
What the drawings help you do
The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package.
This particular reference
OR outline with bubbles on its inputs: the De Morgan form of a NAND used when inputs are active low. An OR outline with a bubble at the output is a NOR, not this NAND equivalent.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: SN74HC00 — NAND gate logic · Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
IEEE / ANSI · OR outline with input bubbles (De Morgan equivalent of NAND)
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · NAND
What it represents
By De Morgan's theorem, a NAND gate is equivalent to an OR gate whose inputs are inverted. Data books and well-drawn schematics use the OR outline with input bubbles when the inputs are active-low signals, so that the drawing reads as any of these low signals produces a high output.
This form is useful where active-low requests or fault lines are combined. Matching bubbles to active-low nets lets a reader follow the logic without mentally inverting each signal, which is the main reason for choosing this representation.
The symbol represents the same physical part as the conventional NAND outline. It does not mean an OR device and inverters are fitted, and the bill of materials will still list a NAND package.
How to read it
- Recognise bubbled inputs on an OR outline as a NAND device.
- Expect the input nets to be active-low signals.
Information to show or reference
- Use this form when the input signals are active low.
- Keep the device reference the same as the NAND package.
- Explain the convention in the sheet legend for unfamiliar readers.
A distinction that matters
An OR outline with a bubble at the output is a NOR, not this NAND equivalent.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC00 — NAND gate logic
Manufacturer NAND gate documentation for the implementing device.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Explains negation and active-low indication at inputs.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
Explore related references
NAND4
ANSI four-input NAND gate
Four-input D-shaped NAND gate with an output bubble; its output goes low only when all four inputs are high.
IEEE / ANSI
NOR
ANSI NOR gate drawn as negative-input AND
AND outline with bubbled inputs, the De Morgan form of a NOR that reads as all inputs low gives a high output.
IEEE / ANSI
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