AND
AND gate
A logic element whose output is true when all stated positive-logic inputs are true.
Schematic
IEEE / ANSI · INH
ANSI inhibit gate (AND with one negated input)
AND outline with a bubble on one input, so that input blocks the output whenever it is active.
In plain English
What does ANSI inhibit gate (AND with one negated input) mean?
An inhibit gate passes one signal only while a second, inhibiting signal is inactive. In distinctive-shape form it is drawn as an AND outline with a bubble on the inhibiting input. It is a very common pattern in interlock logic, where a command is allowed unless a blocking condition is present.
A simple example
On drawings the inhibiting input should be named for the condition that blocks, such as trip active or door open, so that the bubble reads naturally. Where the physical implementation is an AND gate fed by an inverter, the schematic may still use this compact form for clarity.
What the drawings help you do
The symbol does not specify which input has priority in timing. If the inhibiting signal must arrive before the command, a sequencing note or timing element is required.
This particular reference
AND outline with a bubble on one input, so that input blocks the output whenever it is active. A NAND has its bubble at the output; an inhibit gate has its bubble on one input only.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC08 — AND gate logic
IEEE / ANSI · AND outline with a bubble on one input
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · INH
What it represents
An inhibit gate passes one signal only while a second, inhibiting signal is inactive. In distinctive-shape form it is drawn as an AND outline with a bubble on the inhibiting input. It is a very common pattern in interlock logic, where a command is allowed unless a blocking condition is present.
On drawings the inhibiting input should be named for the condition that blocks, such as trip active or door open, so that the bubble reads naturally. Where the physical implementation is an AND gate fed by an inverter, the schematic may still use this compact form for clarity.
The symbol does not specify which input has priority in timing. If the inhibiting signal must arrive before the command, a sequencing note or timing element is required.
How to read it
- Identify which input carries the bubble; that input blocks the output.
- Check whether the implementation includes a separate inverter.
Information to show or reference
- Name the inhibiting input for the blocking condition.
- Place the bubble on the correct input lead.
- Note any timing priority between command and inhibit.
A distinction that matters
A NAND has its bubble at the output; an inhibit gate has its bubble on one input only.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Negation at an input and the resulting internal state.
SN74HC08 — AND gate logic
AND gate documentation for the implementing function.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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