Symbols · AND

AND gate

A logic element whose output is true when all stated positive-logic inputs are true.

Schematic · ANDAND gate: original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

A logic element whose output is true when all stated positive-logic inputs are true.

On a schematic, identify the input signal polarity and the required simultaneous conditions and trace the gate output and its destination. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.

An AND gate combines logical conditions; it does not specify relay-contact current capacity or a safety integrity level.

Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.

How to read it

  • Identify the input signal polarity and the required simultaneous conditions.
  • Trace the gate output and its destination.

Information to show or reference

  • Label the input signal polarity and the required simultaneous conditions.
  • Cross-reference the gate output and its destination.
  • Add the selected device or circuit documentation revision, power/reference connections and project signal convention.

A distinction that matters

An AND gate combines logical conditions; it does not specify relay-contact current capacity or a safety integrity level.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

SN74HC08 — AND gate logic

Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.

Texas Instruments · Public reference checked 14 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 14 October 2026

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