LEVEL
Logic voltage-level translator
Transfers digital information between the documented logic-voltage domains.
Schematic
Symbols · I2C BUF
I2C bus buffer
In plain English
What does I2C bus buffer mean?
An I2C bus buffer separates or supports selected parts of an I2C connection.
A simple example
A design can use a suitable buffer to manage loading between bus segments.
What the drawings help you do
Show the bus segment on each side of the buffer and identify the clock and data paths. Buffers can manage electrical loading, but their permitted direction behaviour and connections vary. They should not be drawn as ordinary logic buffers without checking how they handle the selected I2C bus.
- Bus segment
- A defined section of the shared clock and data connection.
- Pull-up
- A component arrangement that brings an undriven signal towards its selected supply.
Before using this reference
- Identify clock and data on both segments.
- Reference pull-up and loading requirements for each side.
- Check the selected buffer’s permitted bus arrangement.
Does a buffer provide electrical isolation?
Not merely because it separates bus segments electrically for loading purposes. A rated isolation barrier is a different function and must be explicitly identified in the selected device.
Read the source: I2C, I3C and SPI interface functions
Schematic · I2C BUF
A distinction that matters
Buffer behaviour, direction handling and supported bus conditions depend on the selected device.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
I2C, I3C and SPI interface functions
I2C, I3C and SPI interface functions: public technical context for the named function. Product and compliance details remain with the publisher.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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An identified interface converting electrical power between documented circuit forms.
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