DIG-ISO
Capacitive digital isolator
Transfers digital information between separately referenced electrical domains through a capacitive isolation structure.
Schematic
Symbols · LEVEL
Logic voltage-level translator
Transfers digital information between the documented logic-voltage domains.
Schematic · LEVEL
What it represents
Transfers digital information between the documented logic-voltage domains.
On a schematic, identify the two supplies, channel direction and power-sequencing requirements and trace the translated data and receiving-device interface. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
Voltage translation changes logic-domain compatibility; it does not imply galvanic isolation or arbitrary input tolerance.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the two supplies, channel direction and power-sequencing requirements.
- Trace the translated data and receiving-device interface.
Information to show or reference
- Label the two supplies, channel direction and power-sequencing requirements.
- Cross-reference the translated data and receiving-device interface.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
Voltage translation changes logic-domain compatibility; it does not imply galvanic isolation or arbitrary input tolerance.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74LVC1T45 — digital voltage-domain translation
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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