D-FF
Positive-edge D flip-flop
Captures its data input at the documented positive clock edge and retains that digital state.
Schematic
IEC · 1D
IEC D flip-flop (rectangular form)
IEC bistable with a dynamic C1 clock and a 1D data input, storing D on the active clock edge.
In plain English
What does IEC D flip-flop (rectangular form) mean?
In IEC form the D flip-flop is an unlabelled bistable outline with a clock input labelled C1 carrying the dynamic wedge, and a data input labelled 1D to show it is controlled by C1. Asynchronous set and reset inputs are labelled S and R without a number. The two outputs are Q and its complement shown with a negation or polarity mark.
A simple example
TI's overview stresses that a D input always sets the storage element to 1 at its internal 1 state and resets it at 0. On sequential drawings this form makes clocking explicit: anything without the 1 prefix acts immediately, regardless of the clock.
What the drawings help you do
The symbol does not state setup, hold or travel times, and does not define the power-up state unless an I=0 or I=1 additional drawing mark is added.
This particular reference
IEC bistable with a dynamic C1 clock and a 1D data input, storing D on the active clock edge. The IEC D latch has a C1 input without a dynamic mark and is transparent while C1 is active.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74HC74 — positive-edge D flip-flops
IEC · Rectangular bistable with dynamic C1 input and 1D data input
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · 1D
What it represents
In IEC form the D flip-flop is an unlabelled bistable outline with a clock input labelled C1 carrying the dynamic wedge, and a data input labelled 1D to show it is controlled by C1. Asynchronous set and reset inputs are labelled S and R without a number. The two outputs are Q and its complement shown with a negation or polarity mark.
TI's overview stresses that a D input always sets the storage element to 1 at its internal 1 state and resets it at 0. On sequential drawings this form makes clocking explicit: anything without the 1 prefix acts immediately, regardless of the clock.
The symbol does not state setup, hold or propagation times, and does not define the power-up state unless an I=0 or I=1 qualifier is added.
How to read it
- The wedge on C1 indicates edge triggering.
- S and R without numbers are asynchronous.
Information to show or reference
- Label the clock C1 with a dynamic mark.
- Prefix the data input with 1.
- Add I=0 or I=1 where power-up state matters.
A distinction that matters
The IEC D latch has a C1 input without a dynamic mark and is transparent while C1 is active.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Bistable element forms and C dependency with D inputs.
SN74HC74 — positive-edge D flip-flops
D flip-flop device documentation.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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