IEC · NEG-OUT

IEC logic negation at output

Circle on an output edge meaning the internal 1 state of the element produces an external 0.

In plain English

What does IEC logic negation at output mean?

Output negation turns AND into NAND, OR into NOR and a buffer into an inverter. The circle sits where the output line meets the outline and states that the internal 1 state produces the external 0 state. As with input negation, a logic convention must be declared to relate this to voltage levels.

A simple example

Drafters use output negation to avoid drawing separate inverters. When a negated output feeds a negated input on the next element, the two cancel, and reviewers often simplify the drawing by removing both.

Identify the device and formRead the connections and stateCheck the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

What the drawings help you do

The circle carries no information about output drive type or loading. Open-circuit or three-state behaviour needs its own additional drawing mark inside the outline.

This particular reference

Circle on an output edge meaning the internal 1 state of the element produces an external 0. An active-low output triangle states the level directly and is the data-book alternative.

Normally open / normally closed
The contact state in the normal condition defined for the drawing.
Signal
Electrical information passed between devices, rather than necessarily the main power supply.
Rating
A value stating the conditions for which equipment is specified.

Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

IEC · Small circle at the output edge of the outline

Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.

Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.

Schematic · NEG-OUTIEC logic negation at output: original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

Output negation turns AND into NAND, OR into NOR and a buffer into an inverter. The circle sits where the output line meets the outline and states that the internal 1 state produces the external 0 state. As with input negation, a logic convention must be declared to relate this to voltage levels.

Drafters use output negation to avoid drawing separate inverters. When a negated output feeds a negated input on the next element, the two cancel, and reviewers often simplify the drawing by removing both.

The circle carries no information about output drive type or loading. Open-circuit or three-state behaviour needs its own qualifier inside the outline.

How to read it

  • Look for double negations between elements that cancel.
  • Confirm the logic convention declared for the sheet.

Information to show or reference

  • Place the circle at the outline edge, not along the line.
  • Declare the logic convention.
  • Simplify cancelling negations where the hardware allows.

A distinction that matters

An active-low output triangle states the level directly and is the data-book alternative.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

Defines logic negation at an output.

Texas Instruments · Public reference checked 28 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 28 October 2026

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