POSTPONED
IEC postponed output qualifier
Angle mark beside an output showing it changes only when the initiating input returns to its original level.
IEC
IEC · 1J 1K
IEC pulse-triggered (master-slave) JK flip-flop
JK bistable whose outputs carry postponed marks: they change when the clock pulse ends, not at its start.
In plain English
What does IEC pulse-triggered (master-slave) JK flip-flop mean?
A pulse-triggered or master-slave JK flip-flop is drawn with a static C1 input and postponed output marks at Q and its complement. The data must be set up before the clock pulse starts and held while C1 is active; the outputs change when C1 returns to its initial level.
A simple example
Older TTL designs and some relay-logic equivalents use this behaviour. When reviewing, the presence of the postponed mark tells you that J and K must not change during the clock pulse, a stricter rule than for edge-triggered devices.
What the drawings help you do
If the C1 input also carries a dynamic mark, the device is the data lock-out type, which samples on the edge but still postpones the output.
This particular reference
JK bistable whose outputs carry postponed marks: they change when the clock pulse ends, not at its start. The edge-triggered JK flip-flop has a dynamic C1 and no postponed marks.
- Coil
- A wound conductor that can produce a magnetic field when energised.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
IEC · JK bistable with static C1 and postponed-output marks
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · 1J 1K
What it represents
A pulse-triggered or master-slave JK flip-flop is drawn with a static C1 input and postponed output marks at Q and its complement. The data must be set up before the clock pulse starts and held while C1 is active; the outputs change when C1 returns to its initial level.
Older TTL designs and some relay-logic equivalents use this behaviour. When reviewing, the presence of the postponed mark tells you that J and K must not change during the clock pulse, a stricter rule than for edge-triggered devices.
If the C1 input also carries a dynamic mark, the device is the data lock-out type, which samples on the edge but still postpones the output.
How to read it
- Postponed marks at outputs indicate pulse triggering.
- A dynamic C1 together with postponed outputs indicates data lock-out.
Information to show or reference
- Draw postponed marks next to both outputs.
- Show C1 as static unless data lock-out is intended.
- Note data stability requirements.
A distinction that matters
The edge-triggered JK flip-flop has a dynamic C1 and no postponed marks.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Pulse-triggered and data lock-out bistable explanations and postponed output qualifier.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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