AOI
IEC AND-OR-invert element
Two & elements embedded in a ≥1 element with negated output, drawn as one compound IEC AND-OR-invert symbol.
IEC
IEEE / ANSI · AOI
ANSI AND-OR-invert gate
Two D-shaped AND gates feeding a bubbled OR outline, drawn as the distinctive-shape AND-OR-invert function.
In plain English
What does ANSI AND-OR-invert gate mean?
In distinctive-shape drawings the AND-OR-invert function is shown as two or more AND outlines whose outputs enter an OR outline with an output bubble. Data books often draw the AND outlines touching the OR outline to indicate that the whole structure is one gate within one package section.
A simple example
AOI gates are found in older logic boards for multiplexing and for implementing compact sum-of-products expressions. When checking, write the expression as the complement of the OR of each AND term.
What the drawings help you do
The drawing does not reveal whether the device provides expandable inputs or how unused AND inputs must be terminated. Refer to the device documentation for those details.
This particular reference
Two D-shaped AND gates feeding a bubbled OR outline, drawn as the distinctive-shape AND-OR-invert function. The IEC AND-OR-invert uses abutted rectangular & and ≥1 elements instead of distinctive outlines.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: SN74LS51 AND-OR-invert gates
IEEE / ANSI · Two AND outlines feeding an OR outline with output bubble
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · AOI
What it represents
In distinctive-shape drawings the AND-OR-invert function is shown as two or more AND outlines whose outputs enter an OR outline with an output bubble. Data books often draw the AND outlines touching the OR outline to indicate that the whole structure is one gate within one package section.
AOI gates are found in older logic boards for multiplexing and for implementing compact sum-of-products expressions. When checking, write the expression as the complement of the OR of each AND term.
The drawing does not reveal whether the device provides expandable inputs or how unused AND inputs must be terminated. Refer to the device documentation for those details.
How to read it
- Treat touching outlines as one device function, not separate packages.
- Apply the final inversion after the OR.
Information to show or reference
- Keep the AND sections visually grouped with the OR.
- Label each product-term input.
- Terminate unused AND inputs as the device requires.
A distinction that matters
The IEC AND-OR-invert uses abutted rectangular & and ≥1 elements instead of distinctive outlines.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74LS51 AND-OR-invert gates
Manufacturer AND-OR-invert gate documentation.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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