IEEE / ANSI · OE

ANSI three-state inverter with active-low enable

Inverter triangle with an enable lead and bubble entering its side, driving a bus only when enabled.

In plain English

What does ANSI three-state inverter with active-low enable mean?

The three-state inverter is a triangle with an output bubble and a control lead entering the sloping side. A bubble on the control lead means output enable is active low, which is the arrangement on many octal line drivers. When disabled, the output is high impedance.

A simple example

On bus schematics these devices are usually drawn in groups of eight with a shared enable. Drafters should label the enable net once for the group and show which controller output drives it, so the reader can see when the bus is driven.

Identify the device and formRead the connections and stateCheck the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

What the drawings help you do

The symbol does not show bus hold, pull-up or pull-down arrangements needed to keep a disabled bus at a defined level. Those components must be drawn separately.

This particular reference

Inverter triangle with an enable lead and bubble entering its side, driving a bus only when enabled. The non-inverting three-state buffer has no output bubble.

Signal
Electrical information passed between devices, rather than necessarily the main power supply.
Schematic
A drawing showing function and connections rather than physical appearance.

Read the source: SNx4HC240 octal buffers and line drivers with 3-state outputs · Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

IEEE / ANSI · Inverter triangle with bubble and enable lead with bubble on the triangle side

Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted.

Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.

Schematic · OEANSI three-state inverter with active-low enable: original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

The three-state inverter is a triangle with an output bubble and a control lead entering the sloping side. A bubble on the control lead means output enable is active low, which is the arrangement on many octal line drivers. When disabled, the output is high impedance.

On bus schematics these devices are usually drawn in groups of eight with a shared enable. Drafters should label the enable net once for the group and show which controller output drives it, so the reader can see when the bus is driven.

The symbol does not show bus hold, pull-up or pull-down arrangements needed to keep a disabled bus at a defined level. Those components must be drawn separately.

How to read it

  • Check the bubble on the enable lead; it sets the enable polarity.
  • Look for bus-keeper or pull resistors on the driven net.

Information to show or reference

  • Draw the enable lead touching the sloping side of the triangle.
  • Mark enable polarity explicitly.
  • Show the shared enable source for a group of drivers.

A distinction that matters

The non-inverting three-state buffer has no output bubble.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

SNx4HC240 octal buffers and line drivers with 3-state outputs

Manufacturer documentation for inverting octal buffers with three-state outputs.

Texas Instruments · Public reference checked 28 October 2026 · Link only

Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

Three-state output and EN behaviour.

Texas Instruments · Public reference checked 28 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 28 October 2026

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