3STATE
Three-state logic buffer
A digital output stage that can drive logical states or enter its documented high-impedance state.
Schematic
Symbols · BUS-TR
Logic bus transceiver
Drives data between two digital buses according to the selected direction and enable conditions.
Schematic · BUS-TR
What it represents
Drives data between two digital buses according to the selected direction and enable conditions.
On a schematic, identify the A/B bus domains, direction input and output-enable polarity and trace the active direction and high-impedance bus behaviour. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
A transceiver supports a defined direction-control arrangement; it is not automatically a protocol controller or an isolator.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the A/B bus domains, direction input and output-enable polarity.
- Trace the active direction and high-impedance bus behaviour.
Information to show or reference
- Label the A/B bus domains, direction input and output-enable polarity.
- Cross-reference the active direction and high-impedance bus behaviour.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
A transceiver supports a defined direction-control arrangement; it is not automatically a protocol controller or an isolator.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC245 — bidirectional bus transceivers
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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