BUS-TR
Logic bus transceiver
Drives data between two digital buses according to the selected direction and enable conditions.
Schematic
Symbols · 3STATE
Three-state logic buffer
A digital output stage that can drive logical states or enter its documented high-impedance state.
Schematic · 3STATE
What it represents
A digital output stage that can drive logical states or enter its documented high-impedance state.
On a schematic, identify the data input, output-enable polarity and shared-bus ownership and trace the output bus and disabled-state behaviour. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
High impedance differs from driving logical zero; disabled outputs still have device-specific leakage and voltage limits.
Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.
How to read it
- Identify the data input, output-enable polarity and shared-bus ownership.
- Trace the output bus and disabled-state behaviour.
Information to show or reference
- Label the data input, output-enable polarity and shared-bus ownership.
- Cross-reference the output bus and disabled-state behaviour.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
High impedance differs from driving logical zero; disabled outputs still have device-specific leakage and voltage limits.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC125 — three-state buffers
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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