RAM
IEC random-access memory (RAM)
IEC element marked RAM with address grouping, a write control input and A-labelled data inputs and outputs.
IEC
IEC · FIFO
IEC first-in first-out memory (FIFO)
IEC element marked FIFO that stores words in arrival order and reads them out in the same order.
In plain English
What does IEC first-in first-out memory (FIFO) mean?
The FIFO additional drawing mark identifies a first-in first-out memory. There are no address inputs; instead, a write clock stores input words and a read clock delivers them in the same order. Status outputs indicate empty, full and sometimes half-full conditions.
A simple example
FIFOs buffer data between parts of a system that run at different rates, such as a serial receiver and a processor. On a drawing, the status outputs should be traced to see how the system avoids overflow and underflow.
What the drawings help you do
The symbol does not specify depth or whether read and write clocks can be asynchronous. The organisation and device data provide those details.
This particular reference
IEC element marked FIFO that stores words in arrival order and reads them out in the same order. RAM uses addresses; FIFO uses order of arrival.
- Normally open / normally closed
- The contact state in the normal condition defined for the drawing.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
IEC · Rectangular element with FIFO qualifier, write and read clocks and status outputs
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · FIFO
What it represents
The FIFO qualifier identifies a first-in first-out memory. There are no address inputs; instead, a write clock stores input words and a read clock delivers them in the same order. Status outputs indicate empty, full and sometimes half-full conditions.
FIFOs buffer data between parts of a system that run at different rates, such as a serial receiver and a processor. On a drawing, the status outputs should be traced to see how the system avoids overflow and underflow.
The symbol does not specify depth or whether read and write clocks can be asynchronous. The organisation and device data provide those details.
How to read it
- No address inputs: order is implicit.
- Trace full and empty flags to their handling logic.
Information to show or reference
- State depth and width.
- Label write and read clocks.
- Show status outputs and their use.
A distinction that matters
RAM uses addresses; FIFO uses order of arrival.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)
Lists FIFO as a general qualifier.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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