N-DMOS
N-channel depletion MOSFET
An N-channel insulated-gate device that conducts at zero gate-to-source voltage according to its device characteristics.
Schematic
Symbols · N-MOS
N-channel enhancement MOSFET
An insulated-gate transistor whose N-channel conduction is enabled by the documented gate-to-source drive.
Schematic · N-MOS
What it represents
An insulated-gate transistor whose N-channel conduction is enabled by the documented gate-to-source drive.
On a schematic, identify gate, drain, source and any exposed bulk or Kelvin-source terminal and trace the switching path, driver return and body-diode orientation. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
Enhancement mode differs from depletion mode; a MOSFET gate must not be treated as a bipolar base-current input.
Terminal letters describe electrical roles, not package pin numbers. Check the selected public datasheet for the actual pin assignment, polarity and any internally connected terminals before completing the drawing.
How to read it
- Identify gate, drain, source and any exposed bulk or Kelvin-source terminal.
- Trace the switching path, driver return and body-diode orientation.
Information to show or reference
- Label gate, drain, source and any exposed bulk or Kelvin-source terminal.
- Cross-reference the switching path, driver return and body-diode orientation.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
Enhancement mode differs from depletion mode; a MOSFET gate must not be treated as a bipolar base-current input.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
MOSFET families and application documentation
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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