3STATE
Three-state logic buffer
A digital output stage that can drive logical states or enter its documented high-impedance state.
Schematic
Symbols · OC-BUF
Open-collector buffer
Provides a logic output through a transistor pull-down stage requiring the documented external load or pull-up.
Schematic · OC-BUF
What it represents
Provides a logic output through a transistor pull-down stage requiring the documented external load or pull-up.
On a schematic, identify the logic supply, collector output and pull-up/load supply and trace the wired output signal and receiving input. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
An open collector can sink current under its limits; it does not actively drive the high state like a push-pull output.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the logic supply, collector output and pull-up/load supply.
- Trace the wired output signal and receiving input.
Information to show or reference
- Label the logic supply, collector output and pull-up/load supply.
- Cross-reference the wired output signal and receiving input.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
An open collector can sink current under its limits; it does not actively drive the high state like a push-pull output.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74LS07 — open-collector output buffers
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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