Exclusive-OR gate
For two positive-logic inputs, produces a true output when the input states differ.
Computes a parity indication from the defined digital input word.
Computes a parity indication from the defined digital input word.
On a schematic, identify the data width, odd/even convention and cascade mapping and trace the parity output and check/alarm interface. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
A parity check detects a defined class of bit errors; it is not a complete CRC, data-integrity or safety protocol.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
A parity check detects a defined class of bit errors; it is not a complete CRC, data-integrity or safety protocol.
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